© 1999 Scenix Semiconductor, Inc. All rights reserved. - 15 - www.scenix.com SX18AC  / SX20AC / SX28AC Figure 6-1. Data Memory Organization Function Registers INDF RTCC PC STATUS FSR RA RB RC   SRAM
(8 bytes) Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 Bank 0 30 50 70 90 B0 D0 F0 3F 5F 7F 9F BF DF FF 00 07 0F 10 1F FSR    SRAM
(16 bytes each bank 128 bytes total) 7 6 5 4 3 2 1 0 Bank 0 is always accessed for
the lower 16 addresses,
irrespective of the three high-
order bits of FSR. Registers (8 bytes) Bank 0