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IP2022 Data Sheet
7.1.20 T0CFG Register
Timer 0 configuration.
7.1.21 TxCFG1H Register
Timer 1 and 2 configuration.
7
6
3
2
1
0
T0EN
T0PS3:0
Rsrvd. T0IE T0IF
Name
Description
T0EN
Enables Timer 0
0 = Timer 0 disabled
1 = Timer 0 enabled
T0PS3:0
Specifies Timer 0 prescaler divisor
0000 = 1
0001 = 2
0010 = 4
0011 = 8
0100 = 16
0101 = 32
0110 = 64
0111 = 128
1000 = 256
1001 to 1111 = Reserved
T0IE
Timer 0 interrupt enable bit
0 = Timer 0 interrupt disabled
1 = Timer 0 interrupt enabled
T0IF
Timer 0 interrupt flag
0 = No timer overflow has occurred
since this bit was last cleared
1 = Timer overflow has occurred
7
6
5
4
3
2
1
0
Name
Description
OFIE
Timer overflow interrupt enable bit
0 = Overflow interrupt disabled
1 = Overflow interrupt enabled
CAP2IE
or
PWM mode: Compare 2 interrupt enable
bit
CMP2IE
Capture/Compare mode: Capture 2 inter-
rupt enable bit
0 = Capture/Compare 2 interrupt
disabled
1 = Capture/Compare 2 interrupt
enabled
CAP1IE
Capture 1 interrupt enable bit
0 = Capture 1 interrupt disabled
1 = Capture 1 interrupt enabled
CMP1IE
Compare 1 interrupt enable bit
0 = Compare 1 interrupt disabled
1 = Compare 1 interrupt enabled
OFIF
Timer overflow interrupt flag
0 = No timer overflow has occurred
since this bit was last cleared
1 = Timer overflow has occurred