96 www.ubicom.com IP2022 Data Sheet 7.1.18    SPDREG Register Status of clock and PLL settings during run-time. Note: This is a read-only register, use speed instruction
to change settings. 7 6 5 4 3 0 PLL OSC CLK1:0 CDIV3:0 Name Description PLL Run-time control of PLL clock multiplier
operation. If the PLL is not required,
power consumption can be reduced by
disabling it. 0 =   PLL clock multiplier enabled 1 =   PLL clock multiplier disabled OSC Run-time control of OSC oscillator opera-
tion. If the crystal oscillator is not required,
power consumption can be reduced by
disabling it (stops OSC oscillator and
blocks propogation of OSC1 external
clock input). 0 =   OSC oscillator enabled 1 =   OSC oscillator disabled CLK1:0 Selects the system clock source. 00 =   PLL clock multiplier 01 =   OSC oscillator/external clock on OSC1 input 10 =   RTCLK oscillator/external clock on RTCLK1 input 11 =   System clock disabled (off) CDIV3:0 Selects the system clock divisor. 0000 =   1 0001 =   2 0010 =   3 0011 =   4 0100 =   5 0101 =   6 0110 =   8 0111 =   10 1000 =   12 1001 =   16 1010 =   24 1011 =   32 1100 =   48 1101 =   64 1110 =   128 1111 =   System clock disabled (off) Name Description