IP2022 Data Sheet www.ubicom.com 95 7.1.16    SxTCFG Register SERDES TX shift count configuration. 7.1.17    SxTMRH/SxTMRL Register Used to specify the divide value for the OSC clock, post-
PLL  clock  or  SxCLK  input  (specified  in  the  SxMode
register  bits  CLKS1:0,  Section  7.1.11)  to  generate  the
SERDES clock. The effective  divide value  = {SxTMRH,
SxTMRL} + 1. 7 6 5 4 0 GLOBEN  LPBACK  Reserved TXSCNT4:0 Name Description GLOBEN Global enable bit 0 =   Disable SERDES output 1 =   Enable SERDES output LPBACK Loopback enable bit 0 =   Normal operation 1 =   Output is driven into input TXSCNT4:0    Transmit shift count, specifies number of bits to transmit