94 www.ubicom.com IP2022 Data Sheet 7.1.14    SxRSYNC Register SERDES sync pattern configuration. 7.1.15    SxSMASK Register SERDES sync-pattern configuration. 10Base-T mode: USB mode: 7 2 1 0 SYNCPAT7:2 SQUELCHEN  DRIBBITEN Name Description SYNCPAT7:2     Synchronization pattern, bits 7:2 (USB mode only) SQUELCHEN    USB mode: synchronization pattern, bit 1 10Base-T mode: 0 =   Squelch disabled 1 =   Squelch enabled DRIBBITEN USB mode: synchronization pattern, bit
0 10Base-T mode: 0 =   Hardware handles dribble bit 1 =   Software is responsible for han- dling dribble bit 7 6 3 2 1 0 Resrvd.   PREAMCNT3:0   Resrvd.  CONTPAIR  Resrvd. 7 0 MASK7:0 Name Description PREAMCNT3:0 Preamble pair count (10Base-T
mode only). All other encodings are
reserved. 0000 =   24 pairs 0001 =   20 pairs 0010 =   16 pairs 0011 =   12 pairs 0100 =   8 pairs 0101 =   4 pairs CONTPAIR Configures the detection of consecu-
tive pairs of “10” for sync detection. 0 =   Sync detected if 6 "10" pairs + "11”. 1 =   Use PREAMCNT for num- ber of "10" pairs MASK7:0 Mask bits for SxRSYNC (USB mode
only) 0 =   Ignore corresponding bit in SxRSYNC 1 =   Use corresponding bit in search pattern for synchro-
nization byte