IP2022 Data Sheet www.ubicom.com 89 7.1.7 LFSRA Register Linear Feedback Shift Register configuration. 7.1.8 PSPCFG Register Parallel Slave Peripheral configuration. 7 4 3 0 UNIT3:0 INDEX3:0 Name Description UNIT3:0 LFSR unit number (only 0, 1, 2, and 3 are
valid) INDEX3:0 Index to the LFSR register being
accessed (see Table 5-16) 7 6 5 4 3 1 0 PSPEN2 PSPEN1 PSPHEN PSPRDY Res WD  BO Name Description PSPEN2 Port D enable bit 0 =   Port D is available for general- purpose I/O 1 =   Port D is configured for the Parallel Slave Peripheral inter-
face PSPEN1 Port C enable bit 0 =   Port C is available for general- purpose I/O 1 =   Port C is configured for the Parallel Slave Peripheral inter-
face PSPHEN HOLD output enable bit 0 =   HOLD output disabled. Port pin RB5 available for general-pur-
pose I/O. 1 =   HOLD output enabled on port pin RB5. PSPRDY Ready bit 0 =   This bit always reads as zero. 1 =   Write 1 to release HOLD when the IP2022 is ready to allow the
data transfer to complete. WD Watchdog time-out bit. Set at reset, if
reset was triggered by Watchdog Timer
overflow, otherwise cleared. BO Brown-out reset bit. Set at reset, if reset
was triggered by brown-out voltage level
detection, otherwise cleared