IP2022 Data Sheet
www.ubicom.com
87
7.1.5
FCFG Register
Flash configuration.
7
6
5
4
3
2
1
0
FRDTS1:0
FRDTC1:0
FWRT3:0
Name
Description
FRDTS1:0
The core clock frequency is automatically
reduced (if necessary) when executing
out of flash memory to prevent the flash
memory access time from being too short.
The FRDTS1:0 bits specify the minimum
number of system clock cycles required
for instruction execution from flash mem-
ory. The actual execution speed from
flash memory will be the slower of the
speed indicated in the SPDREG register
and the speed specified by the FRDTS1:0
bits.
Setto
this:
If System Clock
Frequency
(MHz) is
System Clock
Cycles For
Each CPU
Core Clock
Cycle
00
0–30
1 cycle
01
30–60
2 cycles
10
60–90
3 cycles
11
90–120
4 cycles
Note
fread = 33ns minimum
FRDTC1:0 The number of CPU core cycles for read-
ing the flash memory using an fread
instruction (or an iread or ireadi
instruction while executing from RAM to
read flash) must be specified to prevent
the flash memory access time from being
too short. Because the CPU core is sub-
ject to changes in speed, the value pro-
grammed in these bits should be appro-
priate for the fastest speed that might be
used (typically, the faster of the main line
code and the interrupt service routine).
The FRDTC1:0 bits specify the number of
CPU core clock cycles required for read
access.
Setto
this:
If Core Clock
Frequency
(MHz) is
Core Clock
Cycles For
Each CPU
Core Clock
Cycle
00
0–30
1 cycle
01
30–60
2 cycles
10
60–90
3 cycles
11
90–120
4 cycles
Note
fread = 33ns minimum
FWRT3:0
The flash memory ferase, fwrite
and ISP bulk erase timing is derived from
the CPU core clock through a program-
mable divider. The FWRT3:0 bits specify
the divisor. The time base must be 1 to 2
microseconds. Below 1 microsecond, the
flash memory will be underprogrammed,
and data retention is not guaranteed.
Above 2 microseconds, the flash memory
will be overprogrammed, and reliability is
not guaranteed.
Set to
this:
If CPU Core
Frequency is:
FWRT
Frequency
Divisor
0000 Reserved
2
0001 Reserved
3
0010 3 - 4 MHz
4
0011 4 - 6 MHz
6
0100 6 - 8 MHz
8
0101 8 - 12 MHz
12
0110 12 - 16 MHz
16
0111 16 - 24 MHz
24
1000 24 - 32 MHz
32
1001 32 - 48 MHz
48
1010 48 - 64 MHz
64
1011 64 - 96 MHz
96
1100 96 - 128 MHz
128
1101 Reserved
192
1110 Reserved
256
1111 Reserved
384
Note:
If FCFG & OSC1 are optimal:
fwrite = 42us
ferase = 10 or 20ms, depending on
FPERT in TRIM0 - (use 20ms)
Name
Description
