86 www.ubicom.com IP2022 Data Sheet 7.1.4 EMCFG Register External memory interface configuration. 7 6 5 3 2 0 EMEN   EMBRT EMWRT2:0 EMRDT2:0 Name Description EMEN Enable external memory interface 0 =   Port C, Port D and RB7:4 avail- able for general-purpose I/O 1 =   Port C, Port D and RB7:4 used for external memory interface
(RD7:0 will immediately become
outputs, ignoring port direction
register value) EMBRT Enable bus release wait state 0 =   No wait state 1 =   One wait state added between a read cycle followed by a write
cycle EMWRT2:0    WR pulse width, in system clock cycles 000 =   1 001 =   2 010 =   3 011 =   4 100 =   5 101 =   6 110 =   7 111 =   8 EMRDT2:0     RD pulse width, in system clock cycles 000 =   1 001 =   2 010 =   3 011 =   4 100 =   5 101 =   6 110 =   7 111 =   8