72 www.ubicom.com IP2022 Data Sheet Input  data  is  shifted  serially  out  of  the  16-bit  DATAIN
register, which can be programmed to  provide the data
LSB-first or MSB-first. Output data is shifted serially LSB-
first into the 16-bit DATAOUT register. A  32-bit  RESCMP  register  (not  shown)  can  be  used  to
compare  the  result  in  the  residue  register  against  an
expected  value. When ML_OUT  is set, residue register
bits 0:31 are compared against RESCMP bits 0:31. When
ML_OUT is clear, residue register bits 39:8 are compared
to RESCMP bits 0:31, respectively. If there are bits in the
residue    register    which    do    not    participate    in    the
programmed    LFSR    operation,     be    sure    that    the
corresponding bits in the RESCMP register are initialized
to the same values as these non-participating bits. Each    LFSR    unit    has    three    configuration    registers
(LFSRCFG1,  LFSRCFG2,  and  LFSRCFG3)  for  various
control  and  status  bits.  The  HL_TRIGGER  bit  in  the
LFSRCFG3  register  controls  whether  operation  of  the
LFSR unit is triggered by a write to the high byte or the low
byte of the DATAIN register (i.e. DATAINH or DATAINL).
The operation then proceeds for some number of cycles
programmed   in   the   SHIFT_COUNT3:0   field   of   the
LFSRCFG1   register.   Completion   of   the   operation   is
indicated when the DONE bit in the LFSRCFG1 register is
set. (Alternatively, software can wait 1 cycle/bit of DATAIN
before reading the result.) An autoloading option is available for each LFSR unit to
load the DATAIN register automatically from the SERDES
RX   buffers   (SxRBUF   register   of   the   corresponding
SERDES   unit).   LFSR0   and   LFSR2   are   paired   with
SERDES1,   and   LFSR1   and   LFSR3   are   paired   with
SERDES2. Three registers in data memory are used to access the
LFSR register banks, as shown in Table 5-15. The LFSRA register is loaded to point to a specific LFSR
unit and a register pair within the unit. The LFSRA register
has the format shown in Figure 5-20 Figure 5-20  LFSRA Register Only 0, 1, 2, and 3 are valid as the UNIT, LFSRA bits 7 and
6  =  don’t  care.  The  valid  encodings  for  the  index  are
shown in Table 5-16. The  LFSR  registers  do  not  support  consecutive  read-
modify-write   operations.   For   example,   the   following
instruction sequence loads unpredictable values: clrb lfsrh,7
clrb lfsrh,4 5.9.1 LFSRCFG1 Register Figure 5-21  LFSRCFG1 Register • SET_RES—set to initialize the residue register to all
ones (write-only, reads as zero). • DONE—clear while the LFSR is busy, set when the
operation is completed. Table 5-15  LFSR Registers in Data Memory Address Name Description 0x23 LFSRH High data byte 0x27 LFSRL Low data byte 0x2B LFSRA Address register 7 4 3 0 UNIT3:0 INDEX3:0 Table 5-16  LFSRA Register INDEX Encoding INDEX3:0    High Byte (LFSRH)    Low Byte (LFSRL) 0x0 DATAINH DATAINL 0x1 DATAOUTH DATAOUTL 0x2 FB2 FB1 0x3 LFSRCFG2 RES4 0x4 RES3 RES2 0x5 RES1 RES0 0x6 FB4 FB3 0x7 LFSRCFG3 DOUT 0x8 LFSRCFG1 POLY4 0x9 POLY3 POLY2 0xA POLY1 POLY0 0xB RESCMP3 RESCMP2 0xC RESCMP1 RESCMP0 All registers initialized to 0x00 upon reset, except RESx
= 0xFF, RESCMPx = 0xFF, and LFSRCFG = 0x10). 7 6 5 4 3 0 Rsvd  SET_RES DONE CMP_RES  SHIFT_COUNT3:0