IP2022 Data Sheet www.ubicom.com 69 5.7.3 Using the A/D Converter The following sequence is recommended: 1.    Set  the  ADCTMR  register  to  the  correct  value  for        the system clock speed.
2.    Load  the  ADCCFG  register  to  specify  the  channel        and set the ADCGO bit. Setting the ADCGO bit en-
       ables and resets the ADC timer.
3.    After a period of time (24 timer overflows = 20.8 µs)        the conversion will complete, the ADCGO bit will be
       cleared, and the ADC timer will be disabled.
4.    A timer-based interrupt service routine can detect or        assume the ADCGO bit has been cleared and read
       the ADC value.
5.    Another load to  the ADCCFG  register  can then  be used to start another conversion. 5.7.4 ADC Result Justification The 10 bits of the ADC value can be mapped to the 16 bits
of the ADCH/ADCL register pair in three different ways, as
shown in Table 5-14. In this table, the numbers in the cells
represent   bit   positions   in   the   10-bit   ADC   value,   Z
represents  zero  (as  opposed  to  bit  position  0),  and  -9
represents the inversion of bit position 9. Table 5-14  Justification of the ADC Value Mode ADCH Register Bits ADCL Register Bits 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Left Justified 9 8 7 6 5 4 3 2 1 0 Z Z Z Z Z Z Right Justified Z Z Z Z Z Z 9 8 7 6 5 4 3 2 1 0 Signed -9 -9 -9 -9 -9 -9 -9 8 7 6 5 4 3 2 1 0