60 www.ubicom.com IP2022 Data Sheet The synchronization pattern register (SxRSYNC) is used
for detecting bit patterns that signal the start of a frame.
For 10Base-T, it is 11010101 (also called the SFD, start of
frame delimiter). The incoming data stream, after passing
through the polarity inversion logic (which can be turned
on  or  off  under  software  control)  is  compared  to  the
synchronization   pattern.   Once   a   match   is   found,   an
internal counter is set to zero and data is shifted into a
shift register. The synchronization matching operation is then disabled until an EOP condition is detected, because
the     synchronization     pattern     potentially     could     be
embedded in the data stream as valid data. When an EOP is detected the SxRCNT register is loaded
with the number of bits actually received, the EOP bit of
the SxINTF register is set, and the data bits are loaded
into the  SxRBUF  register. The  RXBF  bit  in  the  SxINTE
register can be set to enable an interrupt on this event. Table 5-5  10base-T Ethernet Interface Signal and Port Pin Usage     10base-T
Signal Name     SERDES
Signal Name SERDES1
Pin Name SERDES2
Pin Name Direction Description Tx+ SxTXP RE5 RF1 Output Plus-side differential output Tx- SxTXM RE6 RF2 Output Minus-side differential output TxD+ SxTXPE RE4 RF0 Output Plus-side differential output with pre-emphasis TxD- SxTXME RE7 RF3 Output Minus-side differential output with pre-emphasis RxD SxRXD RE3 RF7 Input Receive data (only when comparator is used) Rx+ SxRX+ RG5 RG7 Input Plus-side analog differential input, used for
10base-T Ethernet squelch function Rx- SxRX- RG4 RG6 Input Minus-side analog differential input, used for
10base-T Ethernet squelch function