IP2022 Data Sheet www.ubicom.com 5 1.2.3 Low-Power Support Particular  attention  has  been  paid  to  minimizing  power
consumption. For example, an on-chip PLL allows use of
a lower-frequency external source (e.g., an inexpensive 2
MHz crystal oscillator can be used to produce a 120 MHz
on-chip  clock),  which  reduces  both  power  consumption
and EMI. In addition, software can change the execution
speed of the CPU to reduce power consumption, and a
mechanism  is  provided  for  automatically  changing  the
speed   on   entry  and   return  from  an  interrupt  service
routine.  The  speed  instruction  specifies  power-saving
modes  that include a  clock  divisor  between  1  and  128.
This divisor only affects the clock to the CPU core, not the
timers.  The  speed  instruction  also  specifies  the  clock
source  (OSC1  clock,  RTCLK  oscillator,  or  PLL  clock
multiplier),   and   whether   to   disable   the   OSC1   clock
oscillator  or  the  PLL.  The  speed  instruction  executes
using the current clock divisor. 1.2.4 Memory The IP2022 CPU executes from a 32K × 16 flash program
memory and an 8K × 16 RAM program/data memory. In
addition, the ability to write into the program flash memory
allows flexible  non-volatile data storage.  An  interface  is
available  for  up  to  128K  bytes  of  linearly  addressed
external  memory,  which  can  be  expanded  to  2M  bytes
with   additional   software-based   I/O   addressing.   The
maximum execution rate is 30 MIPS from flash memory
and 120 MIPS from RAM. Speed-critical routines can be
copied  from  the  flash  memory  to  the  RAM  for  faster
execution.  The  IP2022  has  a  mechanism  for  in-system
programming  of  its  flash  and  RAM  program  memories
through a four-wire SPI interface, and software has the
ability  to reprogram the program memories  at run time.
This allows the functionality of a device to be changed in
the field over the Internet. 1.2.5 Instruction Set The    IP2022    instruction    set,    using    16-bit    words,
implements a rich set of arithmetic and logical operations,
including signed and unsigned 8-bit × 8-bit integer multiply
with a 16-bit product. 1.2.6 Other Supported Functions On-chip dedicated hardware also includes a PLL, an 8-
channel 10-bit ADC, general-purpose timers, single-cycle
multiplier,    analog    comparator,    LFSR   units,    external
memory   interface,   brown-out   power   voltage   detector,
watchdog timer, low-power support, multi-source wakeup
capability,   user-selectable   clock   modes,   high-current
outputs, and 52 general-purpose I/O pins. 1.2.7 Programming and Debugging
Support The   IP2022   is   supported   by   leading   third-party   tool
vendors.   On-chip   in-system   debug   capabilities   allow
these tools to provide an integrated software development
environment  that  includes  editor,  assembler,  debugger,
simulator,   and   programmer   tools.   For   example,   the
complete  Red  Hat  GNUPro  tools,  including  C  compiler,
assembler,  linker,  utilities  and  GNU  debugger,  supports
the IP2022. In    addition,    Ubicom    offers    an    integrated    graphical
development   environment   which   includes   an   editor,
project  manager,  graphical  user  interface  for  the  GNU
debugger, device programmer, and ipModule™ configuration tool. Unobtrusive in-system programming is provided through
the ISP interface. There is no need for a bond-out chip for
software  development.  This  eliminates  concerns  about
differences in electrical characteristics between a bond-
out chip and the actual chip used in the target application.
Designers can test and revise code on the same part used
in the actual application.