48 www.ubicom.com IP2022 Data Sheet return the data previously written to the data output buffer
registers,   which   might   not   correspond   to   the   states
actually  present  on  pins  configured  as  inputs  or  pins
forced to another state by an external device. 5.1.5 RxDIR Registers The RxDIR registers select the direction of the port pins.
For each output port pin, clear the corresponding RxDIR
bit. For each input port pin, set the corresponding RxDIR
bit.  Unused  pins  that   are  left   open-circuit   should  be
configured as outputs, to keep them from floating. For example, to configure Port A pins RA3 and RA2 as
outputs and RA1 and RA0 as inputs, the following code
could be used: The second move instruction in this example writes the
RADIR register, located at address 0x022. Because Port
A has only four I/O pins, only the four least significant bits
of this register are used. To  drive  the  RA1  pin  low  and  the  RA0  pin  high,  the
following code then could be executed: The  second  move  instruction  shown  above  writes  the
RAOUT register, located at address 0x021. When reading
the  Port  A  pins  through  the  RAIN  register  (0x020),  the
upper four bits always read as zero. When a write is performed to the RxOUT register of a port
pin  that  has  been  configured  as  an  input,  the  write  is
performed but it has no immediate effect on the pin. If that
pin is later configured as an output, the pin will be driven
with  the  data  that  had  been  previously  written  to  the
RxOUT register. 5.1.6 INTED Register The INTED register consists of 8 edge detection bits that
correspond to the 8 pins of Port B. A set bit in the INTED
register  makes  the  corresponding  port  pin  trigger  on falling edges, while a clear bit makes the pin trigger on
rising edges. 5.1.7 INTF Register The   INTF   register   consists   of   8   interrupt   flags   that
correspond to the 8 pins of Port B. If the trigger condition
for a Port B pin occurs, the corresponding bit in the INTF
register  is  set.  The  bit  is  set  even  if  the  port  pin  is  not
enabled as a source of interrupts. The interrupt service routine (ISR) can check this register
to determine the source of an external interrupt. If a Port
B pin enabled for generating interrupts has a set bit in the
INTF register, software must clear the bit prior to exiting to
prevent repeated calls to the ISR. The Port B interrupt logic is asynchronous (e.g. functions
without a clock in clock-stop mode). A side effect is that
there is a 2-cycle delay between the instruction that clears
a  INTF  bit  and  the  bit  being  cleared.  This  means  that
software   must   clear  the  bit   at  least   2  cycles  before
executing a return from interrupt (reti) instruction. 5.1.8 INTE Register The INTE register consists of 8 interrupt enable bits that
correspond to the 8 pins of Port B. A Port B pin is enabled
as a source of interrupts by setting the corresponding bit
in the INTE register. The pin is disabled as an interrupt
source by clearing the corresponding INTE bit, but takes
up to 1 core clock cycle for the interrupt to be disabled. 5.1.9 Port Configuration Upon Power-Up On  power-up,  all  the  port  control  registers  (RxDIR)  are
initialized to 0xFF. Therefore, each port pin is configured
as   a   high-impedance   input.   This   prevents   any   false
signalling to external components which could occur if the
ports were allowed to assume a random configuration at
power-up. mov w,#0x03 ;load W with the value 0x03 ;(bits 3:2 low, and bits 1:0 ;high) mov 0x022,w ;write 0x03 to RADIR ;register mov w,#0x01 ;load W with the value 0x01 ;(bits 3:1 low, and bit 0
;high) mov 0x021,w ;write 0x01 to RAOUT ;register