IP2022 Data Sheet www.ubicom.com 45 Unlike  RAM,  flash  memory  requires  an  explicit  erase
operation before being written. The ferase instruction is
used   to   erase   a   512-byte   (256-word)   block   of   flash
memory (it brings all bits to 1, see Table 4-9). After the
block has been erased, individual words can be written
with the fwrite instruction (fwrite will not change a
0 to 1). For example, an ferase instruction executed on
any byte address from 0x10000 to 0x100FE erases the
whole    block    spanning    those    addresses.    The    self-
programming  instructions  have  no  access  to  the  flash
memory bits in the configuration block. Rules/Troubleshooting for fread/fwrite/ferase: 1.    Must be executing out of program RAM, with ADDRX         = 01.
2.    FCFG register must be correctly configured.
3.    Wait at least 4 cycles after fread before reading DA-         TAH/L.
4.    No speed commands while fread, fwrite or fe- rase are busy (while XCFG bit 0 = 1). 5.    Do   not   jump   to   flash   memory   while   executing fread/fwrite/ferase. If INTVEC is in flash, en- sure interrupts are disabled. 6. fwrite will not change a 0 to a 1 (use ferase first). 7.    XCFG bit 0 = 0 before execution.
8.    XCFG bit 6 = 1
9.    Make sure interrupts are disabled or that the INTSPD         value matches the SPDREG value.
10.  Wait 1 cycle after changing ADDRX bit 7, ADDRSEL or   EMCFG   bit   7   before   executing   an   fread, fwrite or ferase instruction. 4.7.1 Flash Timing Control The  FCFG  register  controls  the  timing  of  flash  memory
operations.  See  Section  7.1.5  for  a  description  of  the
FCFG register. 4.7.2 Interrupts During Flash Operations Before starting a flash write or erase operation, the FCFG
(see Section 7.1.5) must be set up properly for the current
speed. The CPU core clock is the time base for the flash
write timing compensation, so it is critical that the CPU
core clock speed is not changed during a flash write or
erase operation. Interrupts may be taken during a flash
write or erase operation, if the INTSPD register is set up
so the speed does not change when an interrupt occurs. If the flash read timing compensation is set up for a clock
divisor of 1 (i.e. fastest speed), interrupts will not cause fread/iread   instructions    to    fail,    so    no    special precautions need to be taken to avoid violating the flash
read access time. Table 4-9  ferase Addresses (ADDRX=01) ADDRH (ADDRL=XX) Flash Byte
Addresses 0x00 0x10000 - 0x101FE 0x02 0x10200 - 0x102FE ... ... 0xFE 0x1FE00 - 0x1FFFE