44 www.ubicom.com IP2022 Data Sheet 4.7 Self-Programming Instructions The  IP2022  has  several  instructions  used  to  read  and
write the program RAM and the program flash memory.
These instructions allow the program flash memory to be
read and written through special-purpose registers in the
data memory space, which allows the flash memory to be
used to store both program code and data. Because no special programming voltage is required to
write  to  the  flash  memory,  any  application  may  take
advantage of this feature at run-time. Typical uses include
saving phone numbers and passwords, downloading new
or updated software, and logging infrequent events such
as errors and Watchdog Timer overflow. The self-programming instructions are not affected by the
code-protection flag (the CP bit of the FUSE1 register), so
the  entire  program  memory  is  readable  and  writable  to
any software running on the IP2022. There are seven instructions used for self-programming,
as shown in Table 4-8. Certain uses of the instructions are
not valid. In these cases, the instruction is executed as
though it were a nop instruction (i.e. the program counter
is incremented, but no other registers or bits are affected). Blocking   instructions  take   4  cycles  to   complete,   and
prevent  other  instructions  from  executing.  Non-blocking
instructions occupy the CPU pipeline for only one cycle,
but  they  launch   a  multi-cycle  operation  which  is  not
complete until indicated by the FBUSY bit in the XCFG
register becoming clear. Read and write operations that involve program memory
use two registers. The DATAH/DATAL register is a 16-bit
data buffer used for loading or unloading data in program
memory.  The  ADDRX/ADDRH/ADDRL  register  holds  a
24-bit  byte  address  used  to  specify  the  low-byte  of  the
desired word location in program memory. Like the other pointer   registers   (IPH/IPL,   DPH/DPL,   and   SPH/SPL),
addition to the low byte of the register that results in carry
will cause the high part of the register (ADDRX/ADDRH)
to be incremented. Subtraction from the low byte of the
register that results in borrow will cause the high part of
the register to be decremented. Note:  If  ADDRX  bit  7,  ADDRSEL  or  EMCFG  bit  7  is
modified, it must be immediately followed by a nop, only
if  followed  by  a  fread,  fwrite,  ferase,  iread, iwrite, ireadi or iwritei instruction. Note: If ADDRSEL is modified in the ISR, it must first be
shadowed in software. Note:  ADDRL  bit  0  is  ignored  as  the  A0  address  bit  is
handled automatically in hardware. Software  should  use  the  FBUSY  bit  to  check  that  a
previous  flash memory  operation has  completed  before
executing    another    instruction    that    accesses    flash
memory,  before  jumping  to  or  calling  program  code  in
flash memory, and before changing the CPU core speed.
It  is  not  necessary  to  check  the  FBUSY  bit  if  enough
cycles  are  allowed  for  the  flash  operation  to  complete.
See description of FRDTS1:0, FRDTC1:0 and FWRT3:0
in  Section  7.1.5  for  more  details.  Software  must  not
attempt to execute out of flash memory while the FBUSY
bit is set, because the flash memory is unreadable during
that time. Therefore, code which reads, writes, or erases
flash  memory,  using  the  fread,  fwrite  or  ferase
instructions, must execute from program RAM. The iread
and ireadi instructions are an exception to this rule, only if
INTSPD  <  SPDREG,  or  interrupts  are  disabled  as  the
CPU core speed must not change while a flash memory
read,  write,  or  erase  operation  is  in  progress.  Software
must  wait  at  least  four  cycles  after  an  fread  before
reading DATAH/DATAL.. Table 4-8  Instructions Used for Self-Programming Operation Program RAM Flash External Memory Read  iread (Blocking)
ireadi (Blocking) fread  (Non-Blocking) 1, 2 iread (Non-Blocking) Write  iwrite (Blocking)
iwritei (Blocking) fwrite  (Non-Blocking) 1, 2 iwrite (Non-Blocking) Erase N/A ferase  (Non-Blocking) 1, 2 N/A 1 - Must be executed out of program RAM. 2 - XCFG bit 6 (FWP) needs to be set for these instructions to work. If FWP is cleared, these instructions will
behave as a NOP.