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IP2022 Data Sheet
Re-configurable Over The Internet
Customer application program updatable
Run-time self programming
On-chip in-system programming interface
On-chip in-system debugging support interface
Debugging at full IP2022 operating speed
Programming at device supply voltage level
Real-time emulation, program debugging, and inte-
grated software development environment offered by
leading third-party tool vendors
Complete Software Development Environment
Ubicom's Software Development Kit (SDK) with
IpOS operating system
IpStack Software
TCP/IP protocol stack
NE2000 Ethernet drivers
ipWeb Software - HTTP 1.1 Server
ipFile Flash virtual file system
ipIO Software - Device I/O driven interfaces
MII, I2C, SPI, GPSI, UART
ipModule Software - Pre-built Connectivity Soft-
ware modules
ipEthernet - 10Base-T Ethernet
ipHomePlug - HomePlug power line networking
ipUSB - USB 1.1 Host or Device
ipBlue - Bluetooth
ipWLANstation - 802.11b station (node or bridge)
ipWLANaccesspoint - 802.11b access point
Configuration tool
Integrated tool to support rapid development ef-
forts
Red Hat GNUPro tools including GCC ANSI C compiler
and assembler, linker, utilities, and GNU debugger
Ubicoms Unity IDE including editor, project manager,
graphical user interface to GNU debugger, device
programmer, and ipModule configuration tool
Complete and integrated one-stop phone/email/Web
support from Ubicom on all elements of the development
environment
1.2
Architecture
1.2.1
CPU
The
IP2022
implements
an
enhanced
Harvard
architecture (i.e. separate instruction and data memories)
with independent address and data buses. The 16-bit
program memory and 8-bit dual-port data memory allow
instruction fetch and data operations to occur in parallel.
The advantage of this architecture is that instruction fetch
and memory transfers can be overlapped by a multistage
pipeline, so that the next instruction can be fetched from
program memory while the current instruction is executed
with data from the data memory.
Ubicom has developed a revolutionary RISC-based
architecture that is deterministic, jitter free, and
completely reprogrammable.
The IP2022 implements a four-stage pipeline (fetch,
decode, execute, and write back). At the maximum
operating frequency of 120 MHz, instructions are
executed at the rate of one per 10 ns clock cycle.
1.2.2
Serializer/Deserializers
One of the key elements in optimizing the IP2022 for
device-to-device and device-to-human communication is
the inclusion of two on-chip serializer/deserializer units.
These units support popular communication protocols
such as GPSI, SPI, UART, USB, and 10Base-T Ethernet,
allowing the IP2022 to be used in bridge, access point and
gateway applications.
By performing data serialization and deserialization in
hardware, the CPU bandwidth needed to support serial
communications is greatly reduced, especially at high
baud
rates.
Providing
two
units
allows
easy
implementation of protocol conversion or bridging
functions, such as a USB-to-Ethernet or RS-232 bridges.