IP2022 Data Sheet www.ubicom.com 39 4.5 Key to Abbreviations and Symbols 4.6 Instruction Set Summary Tables Table   4-2   through   Table   4-7   list   all   of   the   IP2022
instructions, organized by category. For each instruction,
the table shows the instruction mnemonic (as written in
assembly   language),   a   brief   description   of   what   the
instruction does, the number of instruction cycles required
for  execution,  the  binary  opcode,  and  the  flags  in  the
STATUS register affected by the instruction. Although  the  number  of  clock  cycles  for  execution  is
typically 1, for the skip instructions the exact number of
cycles  depends  whether  the  skip  is  taken  or  not taken.
Taking the skip adds 1 cycle. The effect of extended skip
instructions (i.e. a skip followed by a loadh, loadl, or page instruction) is not shown. For more detailed description, refer to the Programmer’s
Reference Manual. Symbol Description addr13 13-bit address in assembly language instruc-
tion addr16 16-bit address in assembly language instruc-
tion bit Bit position selector bit in opcode BO Brown-out bit in the PSPCFG register (bit 0) C Carry bit in the STATUS register (bit 0) DC Digit Carry bit in the STATUS register (bit 1) DPH Upper half of data pointer for indirect-with-off-
set addressing (global file register 0x00C) DPL Lower half of data pointer for indirect-with-off-
set addressing (global file register 0x00D) f File register address bit in opcode fr File register field (a 9-bit file register address
specified in the instruction) IPH Indirect Pointer High - Upper half of pointer for
indirect addressing (global file register 0x004) IPL Indirect Pointer Low - Lower half of pointer for
indirect addressing (global file register 0x005) k Constant value bit in opcode n Numerical value bit in opcode PA2:PA0  Page bits in the STATUS register (bits 7:5) PCL Virtual register for direct PC modification (glo-
bal file register 0x009) SPH Upper half of stack pointer for indirect-with-off-
set addressing (global file register 0x006) SPL Lower half of stack pointer for indirect-with-off-
set addressing (global file register 0x007) STATUS   STATUS register (global file register 0x00B) W Working register WD Watchdog Timeout bit in the PSPCFG register
(bit 1) WDT Watchdog Timer counter and prescaler Z Zero bit in the STATUS register (bit 2 , File register/bit selector separator
(e.g. clrb status,z) != inequality # Immediate literal designator in assembly lan-
guage instruction (e.g. mov w,#0xff) #lit8 8-bit literal value in assembly language
instruction & Logical AND (address)  Contents of memory referenced by address ^ Logical exclusive OR | Logical OR || Concatenation Symbol Description