IP2022 Data Sheet www.ubicom.com 37 call   instruction   (a   nop   instruction,   in   the   above example) A program  memory  address  contains  16  bits.  The  jmp
and call instructions specify only the lowest thirteen bits
of the jump/call address. The upper 3 bits come from the
PA2:0  bits  of  the  STATUS  register.  An  indirect  relative
jump can be accomplished by adding the contents of the
W  register  to  the  PCL  register  (i.e.  an  add   pcl,w
instruction). Program  control  instructions  such  as  jmp,  call,  and ret  alter  the  normal  program  sequence.  When  one  of these instructions is executed, the execution pipeline is
automatically cleared of pending instructions and refilled
with   new   instructions,   starting   at   the   new   program
address.  Because  the  pipeline  must  be  cleared,  three
clock cycles are required for execution, one to execute the
instruction and two to reload the pipeline. System Control Instructions A system control instruction performs a special-purpose
operation that sets the operating mode of the device or
reads  data  from  the  program  memory.  Included  in  this
category are the following types of instructions: • speed—changes  the  CPU  core  speed  (for  saving power) • break—enters debug mode • page—writes to the PA2:0 bits in the STATUS regis- ter • loadh/loadl—loads a 16-bit pointer into the DPH and DPL registers • iread—reads  a  word  from  external  memory,  pro- gram flash memory, or program RAM • ireadi—reads a word from program flash memory, or program RAM • iwrite—writes a word to external memory or pro- gram RAM • iwritei—writes a word to program RAM • fread—reads a word from flash program memory • fwrite—writes a word to flash program memory • ferase—erases a block of flash program memory • cwdt—clears the Watchdog Timer 4.3 Instruction Pipeline An  instruction  goes  through  a  four-stage  pipeline  to  be
executed, as shown in Figure 4-11. The first instruction is
fetched from the program memory on the first core clock
cycle. On the second clock cycle, the first instruction is
decoded and a second instruction is fetched. On the third
clock cycle, the first instruction is executed, the second
instruction is decoded, and a third instruction is fetched.
On the fourth clock cycle, the first instruction’s results are
written   to   its   destination,   the   second   instruction   is
executed,  the  third  instruction  is  decoded,  and  a  fourth
instruction is fetched. Once the pipeline is full, instructions
are executed at the rate of one per clock cycle. Instructions that directly affect the contents of the program
counter (such as jumps and calls) require that the pipeline
be  cleared  and  subsequently  refilled.  Therefore,  these
instructions take two additional clock cycles (the PC will
be    changed    during    the    execute    cycle    of    a   jump
instruction). Stage    Core
Cycle 1    Core
Cycle 2    Core
Cycle 3    Core
Cycle 4 Fetch Instruction 1 Instruction 2 Instruction 3 Instruction 4 Decode Instruction 1 Instruction 2 Instruction 3 Execute Instruction 1 Instruction 2 Write Instruction 1 Figure 4-11  Pipeline Execution