IP2022 Data Sheet www.ubicom.com 35 4.2 Instruction Set The instruction set consists entirely of single-word (16-bit)
instructions, most of which can be executed at a rate of
one instruction per clock cycle, for a throughput of up to
120 MIPS when executing out of program RAM. Assemblers     may     implement     additional     instruction
mnemonics for the convenience of programmers, such as
a long jump instruction which compiles to multiple IP2022
instructions  for  handling  the  page  structure  of  program
memory. Refer to the assembler documentation for more
information about any instruction mnemonics implemented in the assembler. 4.2.1 Instruction Formats There are five instruction formats: • Two-operand arithmetic and logical instructions • Immediate-operand arithmetic and logical instructions • Jumps and subroutine calls • Bit operations • Miscellaneous instructions Figure 4-6 shows the two-operand instruction format. The
two-operand instructions perform an arithmetic or logical
operation  between  the  W  register  and  a  data  memory
location specified by the “fr” field. The D bit indicates the
destination   operand.   When   the   D   bit   is   clear,   the
destination operand is the W register. When the D bit is
set, the destination operand is specified by the “fr” field. There are some exceptions to this behavior. The multiply
instructions always load the 16-bit product into the MULH
and W registers. The MULH register receives the upper 8
bits, and the W register receives the lower 8 bits. Traditionally     single-operand     instructions,     such     as
increment, are available in two forms distinguished by the
D  bit.  When  the  D  bit  is  clear,  the  source  operand  is
specified by the “fr” field and the destination operand is
the W register. When the D bit is set, the data memory
location specified by the “fr” field is both the source and
destination operand. Also, there are a few cases of unrelated instructions, such
as clr and cmp, which are distinguished by the D bit. Figure   4-7   shows   the   immediate   operand   instruction
format. In this format, an 8-bit literal value is encoded in the   instruction   field.   Usually   the   W   register   is   the
destination  operand,  however  this  format  also  includes
instructions  that  use  the  top  of  the  stack  or  a  special-
purpose register as the destination operand. Figure 4-8 shows the format of the jump and subroutine
call  instructions.  13  bits  of  the  entry  point  address  are
encoded in the instruction. The remaining three bits come
from the PA2:0 bits of the STATUS register. Figure 4-9 shows the format of the instructions that clear,
set, and test individual bits within registers. The register is
specified by the “fr” field, and a 3-bit field in the instruction
selects one of the eight bits in the register. Figure    4-10    shows    the    format    of    the    remaining
instructions. 4.2.2 Instruction Types The instructions are grouped into the following functional
categories: • Logical instructions • Arithmetic and shift instructions • Bit operation instructions • Data movement instructions • Program control instructions • System control instructions Logical Instructions Each    logic    instruction    performs    a    standard    logical
operation     (AND,     OR,     exclusive     OR,     or     logical
complement) on the respective bits of the 8-bit operands.
The result of the logic operation is written to W or to the
data memory location specified by the “fr” field. 15 10 9 8 0 Opcode D “fr” Field Figure 4-6  Two-Operand Instruction Format 15 8 7 0 Opcode 8-Bit Literal (“#lit8”) Figure 4-7  Immediate-Operand Instruction Format 15 13 12 0 Opcode Entry Point Address (“addr13”) Figure 4-8  Jump and Call Instruction Format 15 12 11 9 8 0 Opcode Bit “fr” Field Figure 4-9  Bit Operation Instruction Format 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 Opcode Figure 4-10  Miscellaneous Instruction Format