32 www.ubicom.com IP2022 Data Sheet 4.0     Instruction Set Architecture The   IP2022   implements   a   powerful   load-store   RISC
architecture   with   a   rich   set   of   arithmetic   and   logical
operations,  including  signed  and  unsigned  8-bit  ×  8-bit
integer multiply with a 16-bit product. The CPU operates on data held in 128 special-purpose
registers,  128  global  registers,  and  3840  bytes  of  data
memory. The special-purpose registers are dedicated to
control and status functions for the CPU and peripherals.
The global registers and data memory may be used for
any  functions  required  by  software,  the  only  distinction
among    them    being    that    the    128    global    registers
(addresses  0x080  to  0x0FF)  can  be  accessed  using  a
direct  addressing  mode.  The  remaining  3840  bytes  of
data  memory  (between  addresses  0x100  and  0xFFF)
must  be  accessed  using  indirect  or  indirect-with-offset
addressing modes. The IPH/IPL register is the pointer for
the  indirect  addressing  mode,  and  the  DPH/DPL  and
SPH/SPL registers are the pointers for the indirect-with-
offset addressing modes. 4.1 Addressing Modes A  9-bit  field  within  the  instruction,  called  the  “fr”  field,
specifies  the  addressing  mode  and  the  address  (in  the
case  of  direct  addressing)  or  the  address  offset  (in  the
case of indirect-with-offset addressing), as shown in Table
4-1 4.1.1 Pointer Registers When an addition or increment instruction (i.e. add, inc, incsz, or incsnz) on the low byte of a pointer register (i.e.  IPL,  DPL,  SPL,  or  ADDRL)  generates  a  carry,  the
high part of the register is incremented. For example, if the
IP register holds 0x00FF and an inc ipl instruction is
executed,    the    register    will    hold    0x0100    after    the
instruction. When a subtraction or decrement instruction
(i.e. sub, subc, dec, decsz, or decsnz) generates a
borrow, the high part of the register is decremented. Note:   Because   carry   and   borrow   are   automatically
handled, the addc and subc instructions are not needed
for arithmetic operations on pointer registers.. Table 4-1  Addressing Mode Summary “fr” Field Mode Syntax Effective Address (EA) Restrictions 0 0000 0000 Indirect mov w,(ip)
mov (ip),w IPH || IPL 0x020 < EA < 0xFFF 0 0nnn nnnn Direct, special-
purpose registers mov w,fr
mov fr,w nnnnnnn 0x002 < EA < 0x07F 0 1nnn nnnn Direct, global
registers mov w,fr
mov fr,w 0x080 + nnnnnnn 0x080 < EA < 0x0FF 1 0nnn nnnn Indirect with offset,
data pointer mov w,offset(dp)
mov offset(dp),w DPH || DPL + nnnnnnn 0x000 < nnnnnnn < 0x07F
0x020 < EA < 0xFFF 1 1nnn nnnn Indirect with offset,
stack pointer mov w,offset(sp)
mov offset(sp),w SPH || SPL + nnnnnnn 0x000 < nnnnnnn < 0x07F
0x020 < EA < 0xFFF