IP2022 Data Sheet
www.ubicom.com
31
3.10.3 TRIM0 Register (factory programmed to $FBFE)
15
12
11
10
9
7
6
5
4
3
2
1
0
SQUELT3:0
SQUELT5 FPERT
CMPT2:0
SQUELT4 VCOT3 SQUELT7:6
VCOT2:0
Figure 3-22 TRIM0 Register
SQUELT7:0
SERDES squelch trim bits
FPERT
Controls flash block pulse erase and bulk erase time, for both self-programming ferase and the FERASE com-
mand from the ISD/ISP interface and bulk erase
0 = 20 ms, if OSC1 frequency and FCFG register settings are optimal.
1 = Reserved - 10ms block erase, 100ms bulk erase
CMPT2:0
Comparator offset trim bits
VCOT3:0
PLL VCO frequency trim bits
