30 www.ubicom.com IP2022 Data Sheet 3.10.2    FUSE1 Register 15 14 13 7 6 5 4 3 2 1 0 CP SYNC Reserved BOR2:0 WDTE WDPS2:0 Figure 3-21  FUSE1 Register CP Clear to enable code protection. Once cleared, this bit cannot be set until the entire device is erased. When
code protection is enabled, program memory reads as all 0 to an external device programmer. This bit does not
affect access to program flash memory made by software, using the iread   and fread instructions. In-system
debugging is not available when code protection is enabled. Code protection does not protect the configuration
block against reading. 0 =  enabled
1 =  disabled SYNC Set to read directly from the port pins through the RxIN register, clear to read through a CPU core clock synchro-
nization register. This bit should be clear if any external devices that can be read from I/O port pins are running
asynchronously to the CPU core clock. See Section 5.1. 0 =  enabled
1 =  disabled BOR2:0 Specifies brown-out voltage level. If AVdd goes below this level, the IP2022 is reset. 000 =  2.30V ± 0.1V
001 =  2.25V ± 0.1V
010 =  2.20V ± 0.1V
011 =  2.15V ± 0.1V
100 =  2.10V ± 0.1V
101 =  2.05V ± 0.1V
110 =  2.00V ± 0.1V 111 =  Disabled, no brown-out reset can occur. WDTE Enables Watchdog Timer in run mode. Disabled in debug mode regardless of this bit. 0 =  disabled
1 =  enabled WDPS2:0 Specifies the Watchdog Timer prescaler divisor. This controls the time period before the Watchdog Timer
expires. If the Watchdog Timer is enabled, software must clear the Watchdog Timer periodically within this time
period to prevent a reset of the IP2022 from occurring. The cwdt instruction or a reset from the RST pin clears
both the Watchdog Timer and its prescaler. 000 =  1 (~20 ms) = 256 x WRC
001 =  2 (~40 ms)
010 =  4 (~80 ms)
011 =  8 (~160 ms)
100 =  16 (~320 ms)
101 =  32 (~640 ms)
110 =  64 (~1280 ms) 111 =  128 (~2560 ms)