IP2022 Data Sheet
www.ubicom.com
3
1.1
Additional Features
Internet Processor Capabilities
Foundation for Highly Flexible Connectivity Solution
•
120 MIPS performance @120 MHz
•
Predictable execution rate for hard real-time applica-
tions
•
Fast and deterministic 3-cycle (25ns @120MHz) in-
ternal interrupt response
•
Hardware save/store of key registers
•
Functions implemented via software tightly coupled
with hardware assist peripherals
Multiple Networking Protocols and Physical Layer
Support Hardware
•
Two full-duplex serializer/deserializer (SERDES)
channels
–
Flexible to support 10Base-T, GPSI, SPI, UART,
USB protocols
–
Two channels for protocol bridging
–
On-chip squelch function for 10Base-T Ethernet
on each SERDES
•
Four hardware LFSR (Linear Feedback Shift Regis-
ter) units
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CRC generation/checking
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Data whitening
–
Encryption
Network Software Package
•
Integrated all software-based TCP/IP protocol stack
and Ethernet MAC
•
RFC-compliant stack
–
Supporting a range of protocol stack layers
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Flash file system
–
Serial I/O and Ethernet drivers
•
Embedded networking application layer
•
IpOS™ operating system
•
IpModule™ configuration tool
Memory
•
64-Kbyte (32K × 16) on-chip program flash memory
•
16-Kbyte (8K × 16) on-chip program/data RAM
•
4-Kbyte on-chip linear-addressed data RAM
•
Self-programming with built-in charge pump: instruc-
tions to read, write, and erase flash memory
•
Addresses up to 2 Mbytes of external memory
CPU Features
•
RISC engine core with DC to 120 MHz operation
•
8.3 ns instruction cycle
•
Compact 16-bit fixed-length instructions
•
Single-cycle instruction execution on most instruc-
tions (3 cycles for jumps and calls)
•
Sixteen-level hardware stack for high-performance
subroutine linkage
•
8 × 8 signed/unsigned single-cycle multiply
•
Pointers and stack operation optimized for C compiler
•
Uniform, linear address space (no register banks)
General-Purpose Hardware Peripherals
•
Two 16-bit timers with 8-bit prescalers supporting:
–
Timer mode
–
PWM mode
–
Capture/Compare mode
•
Parallel host interface, 8/16-bit selectable for use as a
communications coprocessor
•
External memory interface
•
One 8-bit timer with programmable 8-bit prescaler
•
One 8-bit real-time clock/counter with programmable
15-bit prescaler and 32 kHz crystal input
•
Watchdog timer with prescaler
•
10-bit, 8-channel ADC with 1/2 LSB accuracy
•
Analog comparator with hysteresis enable/disable
•
Brown-out minimum supply voltage detector
•
External interrupt inputs on 8 pins (Port B)
Sophisticated
Power
and
Frequency/Clock
Management Support
•
Operating voltage of 2.3V to 2.7V
•
Switching the system clock frequencies between dif-
ferent clock sources
•
On-chip PLL clock multiplier with pre- and post-divider
–
120 MHz on-chip clock from 4 MHz ext. crystal
•
Changing the core clock using a selectable divider
•
Shutting down the PLL and/or the OSC input
•
Dynamic CPU speed control with speed instruction
•
Power-On-Reset (POR) logic
Flexible I/O
•
52 I/O Pins
•
2.3V to 3.6V symmetric CMOS output drive
•
5V-tolerant inputs
•
Port A pins capable of sourcing/sinking 24 mA
•
Optional I/O synchronization to CPU core clock
