IP2022 Data Sheet www.ubicom.com 29 3.10.1    FUSE0 Register 15 14 13 12 11 9 8 6 5 3 2 0 XTAL RTCLK POUT1:0 PIN2:0 Reserved WUDP2:0 WUDX2:0 Figure 3-20  FUSE0 Register XTAL OSC2 crystal drive output (only supports 3-5MHz) 0 =  Enabled
1 =  Disabled RTCLK RTCLK2 crystal drive output 0 =  Enabled
1 =  Disabled POUT1:0 Specifies PLL clock multiplier postscaler divisor 00 =  1
01 =  2
10 =  3
11 =  4 PIN2:0 Specifies PLL clock multiplier prescaler divisor 000 =  1
001 =  2
010 =  3
011 =  4
100 =  5
101 =  6
110 =  7 111 =  8 WUDP2:0 Specifies system clock suspend time during PLL startup (after a speed instruction clears the PLL bit in the SPDREG
register). Cycle counts given are multiples of the Watchdog Timer clock (~15.6KHz). 000 =  140 µs (2 cycles)
001 =  210 µs (3 cycles)
010 =  350 µs (5 cycles)
011 =  630 µs (9 cycles)
100 =  1.19 ms (17 cycles)
101 =  2.31 ms (33 cycles)
110 =  4.55 ms (65 cycles) 111 =  9.03 ms (129 cycles) WUDX2:0 Specifies system clock suspend time during wakeup from clock stop mode (SLEEP), when INTSPD is loaded into
SPDREG from Port B interrupt or RTTMR interrupt. Keeps the OSC1 clock from propogating to the core and RST
asserted until the OSC1 crystal achieves valid signal levels. Cycle counts given are multiples of the Watchdog Timer
clock (~15.6KHz). 000 =  350 µs (5 cycles)
001 =  1.19 ms (17 cycles)
010 =  4.55 ms (65 cycles)
011 =  9.03 ms (129 cycles)
100 =  17.99 ms (257 cycles)
101 =  71.75 ms (1025 cycles)
110 =  573.51 ms (8193 cycles) 111 =  1146.95 ms (16385 cycles)