22 www.ubicom.com IP2022 Data Sheet 3.7.2 Global Interrupt Enable Bit The GIE bit serves two purposes: • Preventing an interrupt in a critical section of mainline
code • Supporting nested interrupts The  GIE  bit  is  automatically  cleared  when  an  interrupt
occurs, to disable interrupts  while the ISR is executing.
The GIE bit is automatically set by the reti instruction to
re-enable interrupts when the ISR returns. To  re-enable  interrupts  during  ISR  execution,  the  ISR
code must first clear the source of the first interrupt. It may
also  be  desirable  to  disable  specific  interrupts  before
setting the GIE bit to provide interrupt prioritization. Even
with GIE deasserted, interrupt triggers are still captured
but an interrupt won’t be triggered until GIE is re-enabled.
Caution must be taken not to exceed the interrupt shadow
register stack depth of 2. Clearing the GIE bit in the ISR cannot be used to globally
disable interrupts so that they remain disabled when the
ISR returns, because the reti instruction automatically
sets the GIE bit. To disable interrupts in the ISR so that
they remain disabled after the ISR returns, the individual
interrupt enable bits for each source of interrupts must be
cleared. 3.7.3 Interrupt Latency The interrupt latency is the time from the interrupt event
occurring  to  first  ISR  instruction  being  latched  from  the
decode to the execute stage. If the interrupt comes from a
Port B input and the SYNC bit in the FUSE1 register is 0,
an  additional  two  core  clock  cycles  of  synchronization
delay are added to the interrupt latency. The ireadi or iwritei instructions are blocking (i.e.
prevent  other  instructions  from  being  executed)  for  4
cycles. The iread   or iwrite instructions are blocking
for 4 cycles while operating on program RAM, and non-
blocking   (single   cycle)   while   operating   on   external
memory. When an interrupt event is triggered, the CPU speed is
changed to the speed specified by the INTSPD register
(the SPDREG register is copied to a shadow register, then
loaded with the value from the INTSPD register). If INTSPD is set the same as SPDREG when an interrupt
occurs, then the interrupt latency is 3 core clock cycles for
synchronous interrupts. If not, then the interrupt latency is
3 core clock cycles, plus the speed change. 3.7.4 Return From Interrupt The   reti   instruction  word  includes  three  bits  which
control its operation, as shown in Table 3-5. The three bits
are  specified  from  assembly  language  in  a  literal  (e.g. reti #0x7 to specify all bits as 1). Updating  the  interrupt  vector  allows  the  programmer  to
implement a sequential state machine. The next interrupt
will  resume  the  code  directly  after  the  previous  reti
instruction. The reti instruction takes 1 cycle to execute, and there
is a further delay of 2 cycles at the mainline code speed to
load the pipeline before the mainline code is resumed. Table 3-4  GIE Bit Handling Event Effect Enter ISR (interrupt) GIE bit is cleared Exit ISR
(reti instruction) GIE bit is set setb xcfg,7 instruction (inside ISR) Enable interrupts for
nested interrupt support clrb xcfg,7 instruction (inside ISR) Nothing, the GIE bit is
already clear setb xcfg,7 instruction (mainline code) Enable interrupts clrb xcfg,7 instruction (mainline code) Disable interrupts Table 3-5  reti Instruction Options Bit Function 2 Reinstate the pre-interrupt speed
1 = enable, 0 = disable 1 Store the PC+1 value in the INTVECH and
INTVECL registers
1 = enable, 0 = disable 0 Add W to the T0TMR register
1 = enable, 0 = disable