20 www.ubicom.com IP2022 Data Sheet the reti instruction. This option can be used to directly
implement a state machine, such as a simple round-robin
scheduling  mechanism  for  a  series  of  interrupt  service
routines (ISRs) in consecutive memory locations. If multiple sources of interrupts have been enabled, the
ISR  must  check  the  interrupt  flags  of  each  source  to
determine the cause of the interrupt. The ISR must clear
the interrupt flag for the source of the interrupt to prevent
retriggering of the interrupt on completion of the ISR (i.e.
execution of the reti instruction). Because the interrupt
logic adds a 2-cycle delay between clearing an interrupt
flag and deasserting the interrupt request to the CPU, the
flag must be cleared at least 2 cycles before the  reti
instruction is taken. When an interrupt is taken, the registers shown in Figure
3-9  are  copied  to  a  shadow  register  set.  Each  shadow
register is actually a 2-level push-down stack, so one level
of interrupt nesting is supported in hardware. The interrupt
processing mechanism is completely independent of the
16-level call/return stack used for subroutines. The  contents  of  the  DATAH  and  DATAL  registers  are
pushed   to   their   shadow   registers   4   cycles   after   the
interrupt  occurs,  to  protect  the  result  of  any  pending iread   instruction.    Therefore,    software    should    not access  the  DATAH  or  DATAL  registers  during  the  first
instruction of an ISR. Figure 3-9  Interrupt Processing (On Entry to the ISR) Note: On entry to the ISR the W, MULH, IPH/IPL, DPH/DPL, SPH/SPL, ADDRSEL and DATAH/DATAL register values
don’t change from their mainline code values. INTVECH/INTVECL Register W Register STATUS Register MULH Register IPH/IPL Register DPH/DPL Register SPH/SPL Register ADDRSEL Register DATAH/DATAL Register 515-068c.eps                   W
Shadow Register 1            STATUS
Shadow Register 1              MULH
Shadow Register 1             IPH/IPL
Shadow Register 1           DPH/DPL
Shadow Register 1           SPH/SPL
Shadow Register 1          ADDRSEL
Shadow Register 1     DATAH/DATAL
Shadow  Register 1 IPCH/IPCL Register PC                   W
Shadow Register 2            STATUS
Shadow Register 2              MULH
Shadow Register 2             IPH/IPL
Shadow Register 2           DPH/DPL
Shadow Register 2           SPH/SPL
Shadow Register 2          ADDRSEL
Shadow Register 2     DATAH/DATAL
Shadow  Register 2 INTSPD Register SPDREG Register           SPDREG
Shadow Register 1           SPDREG
Shadow Register 2 IPCH/IPCL Shadow Register     INTVECH
bits 7:5 copied         GIE
XCFG bit 7 GIE Shadow bit 1 GIE Shadow bit 2 GIE = 0