18 www.ubicom.com IP2022 Data Sheet The actual speed of the CPU is indicated by the SPDREG
register unless the specified speed is faster than the flash
access  time  and  the  program  is  executing  out  of  flash.
When  program  execution  moves  from  program RAM to
program flash memory, the new clock divisor will be the
greater  (slower)  of  the  clock  divisor  indicated  by  the
SPDREG register and the clock divisor required to avoid
violating  the  flash  memory  access  time.  The  SPDREG
register does not indicate if the flash clock divisor is being
used.   The   speed   indicated   by   the   SPDREG   will   be
overridden  only  if  the  speed  is  too  fast  for  the  flash
memory. The FCFG  register  holds  bits  that specify  the minimum
number  of  system  clock  cycles  for  each  flash  memory
cycle (see Section 4.7.1). 3.4.1 Clock Stop Mode (SLEEP) When a  speed  instruction occurs, it is possible for the
CPU clock source to be disabled. The clock to the CPU
core  may  be  disabled  while  the  system  clock  is  left
running, or the system clock may be disabled which also
disables  the  CPU  core  clock.  See  SPDREG,  Section
7.1.18. 3.5 Speed Change The speed  instruction executes using the current clock
divisor.   The   new   clock   divisor   takes   effect   with   the
following  instruction,  as  shown  in  the  following  code
example. The automatic speed changes require a certain amount of
delay to take effect (see Figure 3-4 and Figure 3-16): • Changing the Clock Divisor—there is no delay when the clock divisor is changed (the instruction after the
speed instruction is executed at the new speed). • Changing the Clock Source—the delay is up to one cycle of the slower clock. For example, changing be-
tween 4 MHz and 120 MHz could require up to 0.5 mi-
croseconds. • Turning  on  the  OSC  Clock  Oscillator  (clearing  the
OSC bit in the SPDREG register)—the system clock suspend time is specified in the WUDX2:0 bits in the
FUSE0 register. • Turning on the PLL Clock Multiplier (clearing the PLL
bit in the SPDREG register)—the system clock sus-
pend  time  is  specified  in  the  WUDP2:0  bits  in  the FUSE0 register. If   both   the   OSC   oscillator   and   PLL   are   re-enabled
simultaneously,   the   delay   is   controlled   by   only   the
WUDX2:0  bits.  Bits  in  the  FUSE0  register  are  flash
memory   cells   which   cannot   be   changed   dynamically
during program execution. 3.6 Instruction Timing All  instructions  that  perform  branches  take  3  cycles  to
complete, consisting of 1 cycle to execute and 2 cycles to
load the pipeline. In the case of an automatic speed change, the execution
time  will  be  with  respect  to  the  original  speed  and  the
pipeline load time will be with respect to the new speed. Conditional  branching  is  implemented  in  the  IP2022  by
using  conditional  skip  instructions  to  branch  over  an
unconditional  jump  instruction.  To  support  conditional
branching to other pages, the conditional skip instructions
will  skip  over  two  instructions  if  the  first  instruction  is  a page  instruction.  The  loadh and loadl  instructions also cause an additional instruction to be skipped. When
any of these conditions occur, it is called an extended skip instruction. Skip  instructions  take  1  cycle  if  they  do  not  skip,  or  2
cycles if they skip over one instruction. An extended skip
instruction may skip over more than one loadh, loadl,
or page    instruction,    however    this    operation    is interruptible and does not affect interrupt latency. The iread and iwrite instructions take 4 cycles. The
multiply instructions take 1 cycle. nop ;assume divisor is 4, so this
;instruction takes 4 cycles speed  #0x06 ;change the divisor to 8,
;instruction takes 4 cycles nop ;instruction takes 8 cycles speed  #0x0D ;change the divisor to 1,
;instruction takes 8 cycles nop ;instruction takes 1 cycle Table 3-3  Branch Timing Instruction Execution Time Pipeline Load Time jmp 1 2 call 1 2 ret 1 2 reti 1 2