IP2022 Data Sheet www.ubicom.com 17 3.3.1 Loading the Program RAM Software  loads  the  program  RAM  from  program  flash
memory using the iread/ireadi and iwrite/iwritei instructions. The iread instruction reads the 16-bit word specified by the address held in the
ADDRX/ADDRH/ADDRL  register.  This  word  can  be  in
program    flash    memory,   program   RAM,    or    external
memory.  When  the  iread  instruction  is  executed,  bits
15:8 of the word are loaded into the DATAH register, and
bits 7:0 are loaded into the DATAL register. The address
is a word-aligned byte address (i.e. an address that is zero
in  its  LSB).  The  ireadi  instruction  is  identical  to  the iread  instruction,  except  that  it  also  increments  the address by 2. The iwrite instruction writes the 16-bit word held in the
DATAH/DATAL  registers  to  the  program  RAM  location
specified by the address held in the ADDRX/ADDRH/ADDRL register. The iwritei instruction is identical, except that it also increments the
address    by    2.    For    more    information    about    the iread/ireadi  and  iwrite/iwritei  instructions, see Section 4.7. 3.3.2 Program Counter The  program  counter  holds  the  16-bit  address  of  the
instruction  to  be  executed.  The  lower  eight  bits  of  the
program  counter  are  held  in  the  PCL  register,  and  the
upper eight bits are held in the PCH register. A write to the
PCL  register  will  cause  a  jump  to  the  16-bit  address
specified  by  the  PCH  and  PCL  registers.  If  the  PCL
register is written as the destination of an  add  or  addc
instruction    and    carry    occurs,    the    PCH    register    is
automatically incremented. (This may cause a mismatch
between the PA2:0 bits in the STATUS register and the
current    program    counter,    therefore    it    is    strongly
recommended that direct modification of the PCL register
is only used for jumps within a page.) The PCH register is
read-only. The PA2:0 bits in the STATUS register are not used for
address  generation,  except  when  a  jump  or  subroutine
call instruction is executed. However, when an interrupt is
taken, the PA2:0 bits are automatically updated with the
upper  three  bits  of  the  interrupt  vector.  These  bits  are
restored  from  the  STATUS  shadow  register  when  the
interrupt  service  routine  returns  (i.e.  executes  a  reti
instruction). 3.4 Low Power Support Software can change the execution speed of the CPU to
reduce    power    consumption.    A    mechanism    is    also
provided for  automatically  changing the speed on  entry
and return from the interrupt service routine. The speed
instruction specifies  power-saving modes that include a
clock divisor between 1 and 128. This divisor only affects
the  clock  to  the  CPU  core,  not  the  timers,  SERDES,
external memory or ADC (see Figure 3-16). The  speed
instruction  also  specifies  the  clock  source  (OSC  clock,
RTCLK oscillator, or PLL clock multiplier) and whether to
disable the OSC clock oscillator or the PLL. For maximum power savings when running from the OSC
clock, disable the RTCLK oscillator (RTOSC_EN bit in the
XCFG register), disable the watchdog timer (WDTE bit in
the FUSE1 register), disable the A/D converter (ADCGO
bit    in    the    ADCCFG    register,    disable    the    analog
comparator  (CMPEN  bit  in  the  CMPCFG  register)  and
check that no flash operation is in progress (FBUSY bit in
the  XCFG  register)  before  executing  a  speed  #$FF
instruction. To summarize settings for lowest power: • XCFG bit 4 = 1 • FUSE1 bit 3 = 0 • CMPCFG bit 7 = 0 • ADCCFG bit 3 = 0 • XCFG bit 0 = 0 Note:  Before  executing  the  speed  instruction,  always
remember  to  check  that  the  FBUSY  bit  in  the  XCFG
register    is    clear    and    that   the    FCFG    register    has
appropriate settings for the new clock frequency. The SPDREG register (see Figure 3-4) holds the current settings  for  the  clock  divisor,  clock  source,  and  disable bits.    These    settings    can    be    explicitly    changed    by
executing    a speed   instruction,    and    they    change automatically on interrupts. The SPDREG register is read-
only, and its contents may only be changed by executing
a speed instruction, taking an interrupt, or returning from
an interrupt. Two consecutive speed instructions are not
allowed. The INTSPD register specifies the settings used
during  execution  of  the  interrupt  service  routine.  The
INTSPD register is both readable and writeable. On return from interrupts, the reti instruction includes a
bit   that   specifies   whether   the   pre-interrupt   speed   is
restored or the current speed is maintained (see Table 3-
5).