IP2022 Data Sheet www.ubicom.com 15 The  INTSPD  register  holds  bits  that  control  the  CPU
speed and clock source during interrupt service routines
(it  is  copied  to  the  .  It  has  the  same  format  as  the
SPDREG register. The  XCFG  register  holds  additional  control  and  status
bits, as shown in Figure 3-5. • GIE—global interrupt enable bit. When set, interrupts are enabled. When clear, interrupts are disabled. For
more   information   about   interrupt   processing,   see
Section 3.7. • FWP—flash  write  protect  bit.  When  clear,  writes  to flash   memory   are   ignored.   For   more   information
about  programming  the  flash  memory,  see  Section
4.7. • RTEOS—real-time   timer   oversampling   enable   bit. When set, oversampling is used. For more informa-
tion, see Section 5.3. • RTOSC_EN—RTCLK   oscillator   enable   bit.   When clear, the RTCLK oscillator is operational. When set,
the RTCLK oscillator is turned off. • INT_EN—int instruction interrupt enable bit. When set,  int  instructions  cause  interrupts.  When  clear, int instructions only increment the PC, like nop. • FBUSY—read-only flash memory busy bit. Set while fetching  instructions  out  of  flash  memory  or  while
busy   processing   an   iread,   ireadi,   fwrite, fread or ferase instruction, otherwise clear. For more information about programming the flash mem-
ory, see Section 4.7. The  PCH  and  PCL  register  pair  form  a  16-bit  program
counter. The PCH register is read-only. The PCL register
can be written, but this is not recommended or supported.
The  PCL  register  can  be  used  to  implement  a  lookup table,   by   moving   a   variable   to   the   w   register,   then
executing an add PCL,w instruction. If w=01 when the
add   occurs,   the   the   instruction  after   the  add  will  be
skipped; if w=02, two instructions will be skipped, etc. The  IPCH  and  IPCL  register  pair  specifies  the  return
address when a reti instruction is executed. The  INTVECH  and  INTVECL  register  pair  specifies  the
interrupt vector. It has a default value of 0 following reset.
On   a   return   from   interrupt,   an   option   of   the   reti
instruction allows software to save the incremented value
of  the  program  counter  in  the  INTVECH  and  INTVECL
registers. The  IPH  and  IPL  register  pair  is  used  as  a  pointer  for indirect addressing. For more information about indirect
addressing, see Section 4.1.3. The  DPH  and  DPL  register  pair  and  the  SPH and  SPL
register pair are used as pointer registers for indirect-with-
offset  addressing.  For  more  information  about  indirect-
with-offset addressing, see Section 4.1.4. The SPH and
SPL registers are automatically post-decremented when
storing to memory with a push  instruction, and they are
automatically     pre-incremented     when     reading     from
memory with a pop instruction. The ADDRSEL register holds an index to one of eight 24-
bit pointers used to address program memory. The current
program     memory/external     memory     24-bit     address
selected by the ADDRSEL register is accessable in the
ADDRX (bits 23:16), ADDRH (bits 15:8), and ADDRL (bits
7:0) registers. The upper 5-bits of the ADDRSEL register
are   unused.   All   8   banks   of   24-bits   are   initialized   to
0x000000 upon reset. Program  memory  is  always  read  or  written  as  16-bit
words.  On  reads,  the  data  from  program  memory   is
loaded  into  the  DATAH  and  DATAL  register  pair.  On
writes, the contents of the DATAH and DATAL register pair
are loaded into the program memory. 1011 32 3.75 MHz 1100 48 2.5 MHz 1101 64 1.875 MHz 1110 128 0.9375 MHz 1111 Clock Off 0 MHz 7 6 5 4 3 2 1 0 GIE  FWP  RTEOS  RTOSC_EN  INT_EN Rsvd  FBUSY Figure 3-5  XCFG Register Table 3-2  System Clock Divisor (continued) CDIV3:0 System  Clock
Divisor CPU Core Frequency (if System Clock is 120 MHz)