14 www.ubicom.com IP2022 Data Sheet . • PA2:PA0—Program  memory  page  select  bits. Used to extend the 13-bit address encoded in jump and call
instructions. Modified using the page instruction. • SAR—Skip After Return bit. This bit is set if the core should be in the skipping state, and not set if the core
should not be in the skipping state after the comple-
tion of the return instruction (ret, retnp, or retw
instructions, but not reti). The return instruction will
also clear the SAR control bit to ensure correct behav-
ior after the dynamic jump. • SSF—Shadowed Skipping/not state Flag. Gives the ISR the ability to know if the interrupt occured imme-
diately following a skip instruction. The software can
choose either to clear the SSF flag in the ISR or to
make the first instruction of the context switching code
a nop to flush out the skip state. • Z—Zero bit. Affected by most logical, arithmetic, and data movement instructions. Set if the result was ze-
ro, otherwise cleared. • DC—Digit Carry bit. After addition, set if carry from bit 3   occurred,   otherwise   cleared.   After   subtraction,
cleared if borrow from bit 3 occurred, otherwise set. • C—Carry bit. After addition, set if carry from bit 7 of the result occurred, otherwise cleared. After subtrac-
tion, cleared if borrow from bit 7 of the result occurred,
otherwise  set.  After  rotate  (rr  or  rl)  instructions,
loaded with the LSB or MSB of the operand, respec-
tively. The MULH register receives the upper 8 bits of the 16-bit
product from signed or unsigned multiplication. The lower
8 bits are loaded into the W register. The  SPDREG  register  holds  bits  that  control  the  CPU
speed and clock source settings, and is loaded by using
the   speed   instruction,  as  shown  in  Figure  3-4.  The
SPDREG register is read-only, and its contents may only
be changed by executing a speed instruction, taking an
interrupt,   or   returning   from   an   interrupt.   For   more
information  about  the  speed  instruction  and  the  clock
throttling mechanism, see Section 3.4 and Figure 3-16. Note:  The  speed  instruction  should  be  followed  by  a nop instruction if port b interrupt is used to wake up from sleep mode. • PLL—enable x50 PLL clock multiplier; 0 = enabled.
Power consumption can be reduced by disabling it.
See Figure 3-16. • OSC—enable  OSC  oscillator;  0  =  enabled  (stops
OSC oscillator and blocks propagation of OSC1 ex-
ternal  clock  input).  Power  consumption  can  be  re-
duced by disabling it. • CLK1:0—selects the system clock source, as shown in Table 3-1. See Figure 3-16 for the clock logic. See
Section 7.1.5 (FCFG register, FRDTS1:0 bits) for ex-
ceptions. • CDIV3:0—selects the clock divisor used to generate the CPU core clock from the system clock, as shown
in Table 3-2 (also see Figure 3-16). 7 5 4 3 2 1 0 PA2:0 SAR     SSF Z DC C Figure 3-3  STATUS Register 7 6 5 4 3 0 PLL OSC CLK1:0 CDIV3:0 Figure 3-4  SPDREG Register Table 3-1  CLK1:0 Field Encoding CLK1:0 System Clock Source 00 PLL Clock Multiplier 01 OSC Oscillator/External OSC1 Input 10 RTCLK oscillator/external clock on
RTCLK1 input 11 System Clock Off Table 3-2  System Clock Divisor CDIV3:0 System  Clock
Divisor CPU Core Frequency (if System Clock is 120 MHz) 0000 1 120 MHz 0001 2 60 MHz 0010 3 40 MHz 0011 4 30 MHz 0100 5 24 MHz 0101 6 20 MHz 0110 8 15 MHz 0111 10 12 MHz 1000 12 10 MHz 1001 16 7.5 MHz 1010 24 5 MHz