IP2022 Data Sheet www.ubicom.com 13 • Watchdog timer reset • In-system debugging/programming interface reset An on-chip PLL clock multiplier (x50) enables high-speed
operation  (up  to  120  MHz)  from  a  slow-speed  external
clock input, crystal, or ceramic resonator. A CPU clock-
throttling   mechanism   allows   fine   control   over   power
consumption  in  modes  that  do  not  require  maximum
speed, such as waiting for an interrupt. The IP2022 has a mechanism for in-system programming
of its flash and RAM program memories through a four-
wire SPI interface. This provides easy programming and
reprogramming of devices on assembled circuit boards. In
addition,   the   flash   memory   can   be   programmed   by
software  at  run  time,  for  example  to  store  user-specific
data  such  as  phone  numbers  and  to  receive  software
upgrades downloaded over the Internet. The IP2022 also
has   an   on-chip   debugging   facility   which   makes   the
internal   operation   of   the   chip   visible   to   third-party
debugging tools. 3.1 CPU Registers Figure  3-2  shows  the  CPU  registers,  which  consist  of
seven 8-bit registers, seven 16-bit registers, and one 24-
bit register. The 16-bit registers are formed from pairs of
8-bit registers, and the 24-bit register is formed from three
8-bit registers. For the register quick reference guide, see
Section 7.0. Figure 3-2  CPU Registers The  W  or  working  register  is  used  as  the  source  or
destination  for  most  arithmetic,  movement,  and  logical
instructions. The  STATUS  register  holds  the  condition  flags  for  the
results of arithmetic and logical operations, the page bits
(used  for  jumps  and  subroutine  calls),  and  bits  which
indicate  the  skipping  state  of  the  core  and  control  of
continuation  skip  after  return  from  interrupt.  Figure  3-3
shows the assignment of the bits in the STATUS register. INTVECH/INTVECL Register * W Register STATUS Register MULH Register SPDREG Register IPH/IPL Register DPH/DPL Register SPH/SPL Register DATAH/DATAL Register * ADDRX/ADDRH/ADDRL Register 515-040a.eps IPCH/IPCL Register * 7 15 0 0 Interrupt Registers 15 0 Pointer Registers 15 0 Program Memory/External Memory Interface Registers PCH/PCL Register 15 XCFG Register INTSPD Register ADDRSEL Register 23 7 * Low byte doesn’t carry to high byte