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IP2022 Data Sheet
8.3
AC Specifications
Operating Temperature: -40°C < Ta < +85°C
3. Vdd must start rising from Vss to ensure proper Power-On-Reset when relying on the internal Power-On-Reset
circuitry.
8.4
Comparator DC and AC Specifications
Operating Temperature: -40°C < Ta < +85°C.
Symbol
Parameter
Min
Typ
Max
Units
Conditions
Fcore
CPU core clock frequency
0
120
MHz
Execution from
program RAM
Fflash
CPU core clock frequency
0
30
MHz
Execution from
program flash
Fsys
System clock frequency
0
120
MHz
Fosc
External clock frequency on OSC1
0
120
MHz
Foscr
External clock frequency on RTCLK1
0
120
MHz
Fxo
Crystal oscillator frequency, OSC
3
5
MHz
Ext. crystal or res-
onator, ±100 ppm
Fpll
PLL input frequency, after predivider
3
5
MHz
Fxr
Crystal oscillator frequency, RTCLK
32.765
32.768
32.771
kHz
Ext. crystal
Tosl, Tosh Clock in (OSC1) low or high time
3
ns
Trl, Trh
Clock in (RTCLK1) low or high time
3
ns
SVdd
DVdd slew rate to ensure Power-On
reset
0.05
V/ms
See note 3.
Parameter
Min
Typ
Max
Units
Conditions
Input offset voltage
±10
±25
mV
CMPT2:0 bits in TRIM0 reg-
ister are 111
Hysteresis, rising or falling edge
20
50
80
mV
Bandwidth
15
MHz
min. 100 mV peak-to-peak
Response time
100
ns
Voverdrive = 50 mV
Does not include compara-
tor mode entry stabilization
time
Time from enabling comparator until
output is valid
2000
ns
Input voltage range
0.1
AVdd - 0.1
V