102 www.ubicom.com IP2022 Data Sheet 7.1.25    TCTRL Register Timer 1 and 2 configuration. 7.1.26    XCFG Register Extra configuration bits for various functions. 7 6 5 4 3 2 1 0 0 0 T2IE    T1IE 0 0 T2RST  T1RST Name Description T2IE Timer 2 interrupt enable 0 =   Timer 2 interrupt disabled 1 =   Timer 2 interrupt enabled T1IE Timer 1 interrupt enable 0 =   Timer 1 interrupt disabled 1 =   Timer 1 interrupt enabled T2RST Timer 2 reset bit. This bit always reads as
zero. 0 =   Writing 0 to this bit has no effect. 1 =   Writing 1 to this bit clears Timer 2. T1RST Timer 1 reset bit. This bit always reads as
zero. 0 =   Writing 0 to this bit has no effect. 1 =   Writing 1 to this bit clears Timer 1. 7 6 5 4 3 2 1 0 GIE   FWP  RTEOS RTOSC_EN INT_EN  Rsvd  FBUSY Name Description GIE Global interrupt enable bit 0 =   Interrupts disabled 1 =   Interrupts enabled FWP Flash write protect bit. This bit only
affects operation of the flash fwrite
and ferase self-programming instruc-
tions, not programming through the
ISD/ISP interface. 0 =   Writes to flash memory dis- abled 1 =   Writes to flash memory enabled RTEOS Real-time timer oversampling bit 0 =   Oversampling disabled 1 =   Oversampling enabled RTOSC_EN RTCLK oscillator enable bit 0 =   RTCLK oscillator is operational 1 =   RTCLK oscillator turned off INT_EN int instruction interrupt enable bit 0 =   int instructions only incre- ment the PC, like nop 1 =   int instructions cause inter- rupts FBUSY Flash memory busy bit (read-only).
For more information about programming
the flash memory, see Section 4.7. 0 =   Flash memory is idle 1 =   Fetching instructions out of flash memory or busy process-
ing an iread, ireadi, fwrite, fread or ferase instruction