98 www.ubicom.com IP2022 Data Sheet 7.3.13    SxTCFG Register 7.3.14    SPDREG Register This  is  a  read-only  register,  use  speed  instruction  to
change settings. 7.3.15    STATUS Register 7 6 5 4 0 SEREN   Reserved  TPOREV TXSCNT4:0 Name Description SEREN SERDES enable bit 0 =   SERDES disabled
1 =   SERDES enabled TPOREV Transmit data polarity reversal select 0 =   Data polarity uninverted
1 =   Data polarity inverted TXSCNT4:0 Transmit shift count, specifies number of
bits to transmit 7 6 5 4 3 0 PLL OSC CLK1:0 CDIV3:0 Name Description PLL Controls PLL clock multiplier operation. If
the PLL is not required, power consump-
tion can be reduced by disabling it. 0 =   PLL clock multiplier enabled
1 =   PLL clock multiplier disabled OSC Controls OSC oscillator operation. If the
oscillator is not required, power consump-
tion can be reduced by disabling it. 0 =   OSC oscillator enabled
1 =   OSC oscillator disabled CLK1:0 Selects the system clock source. 00 =   PLL clock multiplier
01 =   OSC oscillator/external clock             on OSC1 input
10 =   RTCLK oscillator/external clock             on RTCLK1 input
11 =   System clock disabled (off) CDIV3:0 Selects the system clock divisor. 0000 =   1
0001 =   2
0010 =   3
0011 =   4
0100 =   5
0101 =   6
0110 =   8  0111 =   10
1000 =   12
1001 =   16
1010 =   24
1011 =   32
1100 =   48
1101 =   64 1110 =   128
1111 =   System clock disabled (off) 7 5 4 3 2 1 0 PA2:0 WD BO Z DC C Name Description PA2:0 Program memory page select bits. Used
to extend the 13-bit address encoded in
jump and call instructions. Modified using
the page instruction. WD Watchdog time-out bit. Set at reset, if
reset was triggered by Watchdog Timer
overflow, otherwise cleared. 0 =   Last reset was not caused by a           Watchdog Timer overflow.
1 =   Last reset was caused by a Watchdog Timer overflow. Name Description