IP2022 Data Sheet www.ubicom.com 95 7.3.6 LFSRA Register (LFSR Address) 7.3.7 PSPCFG Register (Parallel Slave Pe-
ripheral Configuration) 7.3.8 RTCFG  Register  (Real-Time  Timer
Configuration) 7 4 3 0 UNIT3:0 INDEX3:0 Name Description UNIT3:0 LFSR unit number (only 0, 1, 2, and 3 are
valid) INDEX3:0 Index to the LFSR register being
accessed (see Table 5-15) 7 6 5 4 3 0 PSPEN2 PSPEN1 PSPHEN PSPRDY Reserved Name Description PSPEN2 Port D enable bit 0 =   Port D is available for general-           purpose I/O
1 =   Port D is configured for the Parallel Slave Peripheral inter-
face PSPEN1 Port C enable bit 0 =   Port C is available for general-           purpose I/O
1 =   Port C is configured for the Parallel Slave Peripheral inter-
face PSPHEN HOLD output enable bit 0 =   HOLD output disabled. Port pin           RB5 available for general-pur-
          pose I/O.
1 =   HOLD output enabled on port pin RB5. PSPRDY Ready bit 0 =   This bit always reads as zero.
1 =   Write 1 to release HOLD when the IP2022 is ready to allow the
data transfer to complete. 7 6 3 2 1 0 RTEN RTPS3:0 RTSS   RTIE    RTIF Name Description RTEN Real-Time Timer enable bit 0 =   Real-Time Timer disabled
1 =   Real-Time Timer enabled RTPS3:0 Real-Time Timer prescaler divisor 0000 =   1
0001 =   2
0010 =   4
0011 =   8
0100 =   16
0101 =   32
0110 =   64  0111 =   128
1000 =   256
1001 =   512
1010 =   1024
1011 =   2048
1100 =   4096
1101 =   8192 1110 =   16384
1111 =   32768 RTSS Real-Time Timer clock source select 0 =   pre-PLL clock
1 =   external RTCLK RTIE Real-Time Timer interrupt enable bit 0 =   Real-Time Timer interrupt dis-           abled
1 =   Real-Time Timer interrupt enabled