94 www.ubicom.com IP2022 Data Sheet 7.3.5 INTSPD Register FWRT3:0 The flash memory erase and write timing
is derived from the CPU core clock
through a programmable divider. The
FWRT3:0 bits specify the divisor. The time
base must be 1 to 2 microseconds. Below
1 microsecond, the flash memory will be
underprogrammed, and data retention is
not guaranteed. Above 2 microseconds,
the flash memory will be overpro-
grammed, and reliability is not guaran-
teed. 0000 =   2
0001 =   3
0010 =   4
0011 =   6
0100 =   8
0101 =   12
0110 =   16  0111 =   24
1000 =   32
1001 =   48
1010 =   64
1011 =   96
1100 =   128
1101 =   192 1110 =   256
1111 =   384 Name Description 7 6 5 4 3 0 PLL OSC CLK1:0 CDIV3:0 Name Description PLL Controls PLL clock multiplier operation. If
the PLL is not required, power consump-
tion can be reduced by disabling it. 0 =   PLL clock multiplier enabled
1 =   PLL clock multiplier disabled OSC Controls OSC oscillator operation. If the
oscillator is not required, power consump-
tion can be reduced by disabling it. 0 =   OSC oscillator enabled
1 =   OSC oscillator disabled CLK1:0 Selects the system clock source. 00 =   PLL clock multiplier
01 =   OSC oscillator/external clock             on OSC1 input
10 =   RTCLK oscillator/external clock             on RTCLK1 input
11 =   System clock disabled (off) CDIV3:0 Selects the system clock divisor. 0000 =   1
0001 =   2
0010 =   3
0011 =   4
0100 =   5
0101 =   6
0110 =   8  0111 =   10
1000 =   12
1001 =   16
1010 =   24
1011 =   32
1100 =   48
1101 =   64 1110 =   128
1111 =   System clock disabled (off)