IP2022 Data Sheet www.ubicom.com 93 7.3.3 EMCFG Register 7.3.4 FCFG Register (Flash Configuration) 7 6 5 3 2 0 EMEN   EMBRT EMWRT2:0 EMRDT2:0 Name Description EMEN Enable external memory interface 0 =    Port C and Port D available for           general-purpose I/O
1 =    Port C and Port D used for exter- nal memory interface EMBRT Enable bus release wait state 0 =    No wait state
1 =    One wait state added between a read cycle followed by a write
cycle EMWRT2:0 WR pulse width, in CPU core clock cycles 000 =    1
001 =    2
010 =    3
011 =   4
100 =    5
101 =    6
110 =   7 111 =    8 EMRDT2:0 RD pulse width, in CPU core clock cycles 000 =    1
001 =    2
010 =    3
011 =   4
100 =    5
101 =    6
110 =   7 111 =    8 7 6 5 4 3 2 1 0 FRDTS1:0 FRDTC1:0 FWRT3:0 Name Description FRDTS1:0 The system clock frequency is automati-
cally reduced (if necessary) when execut-
ing out of flash memory to prevent the
flash memory access time from being
exceeded. The FRDTS1:0 bits specify the
minimum number of system clock cycles
required for instruction execution from
flash memory. The actual execution
speed from flash memory will be the
slower of the speed indicated in the
SPDREG register and the speed specified
by the FRDTS1:0 bits. 00 =   1 cycle
01 =   2 cycles
10 =   3 cycles
11 =   4 cycles FRDTC1:0 The number of CPU core cycles for read-
ing the flash memory using an iread
instruction must be specified to prevent
the flash memory access time from being
exceeded. Because the CPU core is sub-
ject to changes in speed, the value pro-
grammed in these bits should be
appropriate for the fastest speed that
might be used (typically, the faster of the
main line code and the interrupt service
routine). The FRDTC1:0 bits specify the
number of CPU core clock cycles required
for read access. 00 =   1 cycle
01 =   2 cycles
10 =   3 cycles
11 =   4 cycles