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IP2022 Data Sheet
0x064
S1TCFG
SERDES 1
transmit configu-
ration
00000000
0x060
S1TMRH
SERDES 1
clock timer reg-
ister (high byte)
00000000
0x061
S1TMRL
SERDES 1
clock timer reg-
ister (low byte)
00000000
0x07B
S2INTE
SERDES 2
interrupt enable
bits
00000000
0x07A
S2INTF
SERDES 2 sta-
tus/interrupt
flags
00000000
0x07C
S2MODE
SERDES 2
serial
mode/clock
select register
00000000
0x076
S2RBUFH
SERDES 2
receive buffer
(high byte)
Undefined
0x077
S2RBUFL
SERDES 2
receive buffer
(low byte)
Undefined
0x078
S2RCFG
SERDES 2
receive configu-
ration
00000000
0x075
S2RCNT
SERDES 2
received bit
count (actual)
(read-only)
00000000
0x079
S2RSYNC
SERDES 2
receive bit sync
pattern
00000000
0x07D
S2SMASK
SERDES 2
receive sync
mask
00000000
0x072
S2TBUFH
SERDES 2
transmit buffer
(high byte)
Undefined
0x073
S2TBUFL
SERDES 2
transmit buffer
(low byte)
Undefined
Table 7-2 Register Addresses and Reset State (contin-
Address
Name
Description
Reset
Value
0x074
S2TCFG
SERDES 2
transmit configu-
ration
00000000
0x070
S2TMRH
SERDES 2
clock timer reg-
ister (high byte)
00000000
0x071
S2TMRL
SERDES 2
clock timer reg-
ister (low byte)
00000000
0x00E
SPDREG
Current speed
(read-only)
10010011
0x006
SPH
Stack Pointer
(high byte)
00000000
0x007
SPL
Stack Pointer
(low byte)
00000000
0x00B
STATUS
STATUS register On POR or
RST Reset:
11100000
OnBrown-out
Reset:
11101000
On WDT
Overflow:
11110000
0x043
T0CFG
Timer 0 configu-
ration register
00000000
0x042
T0TMR
Timer 0 value
00000000
0x046
T1CAP1H
Timer 1 Capture
1 register (high
byte, read-only)
00000000
0x047
T1CAP1L
Timer 1 Capture
1 register (low
byte, read-only)
00000000
0x048
T1CAP2H
or
T1CMP2H
Timer 1 Capture
2 (high byte)
Timer 1 Com-
pare 2 (high
byte)
00000000
0x049
T1CAP2L
or
T1CMP2L
Timer 1 Capture
2 (low byte)
Timer 1 Com-
pare 2 (low byte)
00000000
Table 7-2 Register Addresses and Reset State (contin-
Address
Name
Description
Reset
Value