IP2022 Data Sheet
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73
5.7.3
Using the A/D Converter
The following sequence is recommended:
1. Set the ADCTMR register to the correct value for
the system clock speed.
2. Load the ADCCFG register to specify the channel
and set the ADCGO bit. Setting the ADCGO bit en-
ables and resets the ADC timer.
3. After a period of time (12 timer overflows = 20.8 µs)
the conversion will complete, the ADCGO bit will be
cleared, and the ADC timer will be disabled.
4. A timer-based interrupt service routine can detect or
assume the ADCGO bit has been cleared and read
the ADC value.
5. Another load to the ADCCFG register can then be
used to start another conversion.
5.7.4
A/D Converter Registers
ADCTMR Register
The ADCTMR register is used to specify the number of
system clock cycles required for a delay of 1736 ns, which
is used to provide the 576 kHz (48 kHz × 12) clock period
reference clock for the A/D converter.
At a system clock frequency of 100 MHz, the timer register
should be set to 174 (100 MHz/0.576 MHz). The minimum
value that may be loaded into the ADCTMR register is 2,
so the system clock must be at least 24 times the ADC
sampling frequency for the ADC to function.
ADCCFG Register
The A/D converter configuration register (ADCCFG)
provides the control and status bits for the A/D converter,
as shown in Figure 5-19.
•
ADCREF—set to use an external reference voltage,
clear to use AVdd as the reference voltage.
•
ADCJST—00 selects right justified, 01 selects signed,
and 10 selects left justified. 11 is reserved.
•
ADCGO—set to start a conversion. When the bit be-
comes clear, the conversion is complete.
•
ADCS2:0—specifies the bit number of the Port G pin
used as the analog input.
Table 5-13 Justification of the ADC Value
Mode
ADCH Register Bits
ADCL Register Bits
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Left Justified
9
8
7
6
5
4
3
2
1
0
Z
Z
Z
Z
Z
Z
Right Justified
Z
Z
Z
Z
Z
Z
9
8
7
6
5
4
3
2
1
0
Signed
-9
-9
-9
-9
-9
-9
-9
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
0
ADCREF
ADCJST Reserved ADCGO
ADCS2:0
Figure 5-19 ADCCFG Register
