IP2022 Data Sheet www.ubicom.com 69 5.6.11    SxINTE Register The SxINTE register has the same format as the SxINTF
register.  For  each  condition  indicated  by  a  flag  in  the
SxINTF   register,   setting   the   corresponding   bit   in   the
SxINTE register enables the interrupt for that condition.
Figure 5-15 shows the interrupt logic for the two SERDES
units. Figure 5-15  SERDES Interrupt Logic RXBF Receive buffer full interrupt flag 0 =    Receive buffer has not been           full since this bit was last
          cleared
1 =    Receive buffer has been full RXXCRS In 10Base-T mode, set if signal
energy is detected but no link pulse
is detected 0 =    No signal energy without link           pulse has been detected
          since this bit was last cleared
1 =    Signal energy without a link pulse has been detected Name Description 515-041.eps S1INTF Register S1INTE Register Serializer/
Deserializer
Interrupt S0INTF Register S0INTE Register