IP2022 Data Sheet www.ubicom.com 67 5.6.6 SxRCFG Register 5.6.7 SxRCNT Register 5.6.8 SxTBUFH/SxTBUFL Register 16-bit register pair for loading transmit data. The TXBE bit
in the SxINTF register indicates when the data has been
transmitted and the register is ready to be loaded with new
data. If the corresponding bit in the SxINTE register is set,
an interrupt is generated. 7 6 5 4 0 MASSEL   SYNCDETEN   RPOREV RXSCNT4:0 Name Description MASSEL 10Base-T mode:           0 =    Normal polarity detected
          1 =    Reverse polarity detected
GPSI or SPI mode: 0 =    Slave mode
1 =    Master mode SYNCDETEN Synchronization byte detection enable
(USB mode only) 0 =    Synchronization byte detec-           tion enabled
1 =    Synchronization byte detec- tion disabled RPOREV Receive data polarity reversal select 0 =    Data polarity uninverted
1 =    Data polarity inverted RXSCNT4:0 Receive shift count, specifies number
of bits to receive 7 6 5 4 0 BITORDER    RxCRSCTRL1:0 RXACNT4:0 Name Description BITORDER Bit order for transmit and receive 0 =    LSB first
1 =    MSB first RxCRSCTRL1:0 Carrier sense status and interrupt
control
0x =    No interrupt. Software can             poll the RXXCRS bit in the
            SxINTF register for carrier
            status.
10 =    Interrupt on carrier detection
11 =    Interrupt on loss of carrier RXACNT4:0 Receive shift count, actual number
of bits received (read-only). Excep-
tions occur during the last transfer: RXACNT = 0 if bit count is
less than 8
RXACNT = 8 if bit count is
greater than or equal to 8, but
less than 16
RXACNT = 16 if bit count is
greater than or equal to 16
and the RXSCNT4:0 field in
the SxRCFG register is 16