62 www.ubicom.com IP2022 Data Sheet Figure  5-12  shows  the  clock/data  separation  and  EOP
detection  logic  of  a  SERDES  unit.  In  USB  mode,  the
SxRXD input carries the data received from an external
transceiver. The SxRXP and SxRXM pins correspond to
the  differential  inputs  of  the  USB  bus.  Providing  both
inputs    allows    sensing    of    an    End-of-Packet    (EOP)
condition.  The  SxRXD  input  is  also  used  for  interfaces
with   single-ended   input   (i.e.   GPSI,   SPI,   and   UART
modes), in which case the clock/data separation circuit is
bypassed.   For   10Base-T   Ethernet,   a   differential   line
receiver is provided. The   SxRXP   and   SxRXM   pins   should   not   both   be
grounded or left floating, otherwise a false EOP condition
may  be  detected.  For  those  interfaces  which  sense  an
EOP condition (i.e. any mode except UART), at least one
of these inputs should be driven high to prevent spurious
EOP events. The synchronization pattern register (SxRSYNC) is used
for USB and 10Base-T protocols for detecting bit patterns
that signal the start of a frame. For USB, this register is
loaded with 00000001, while for 10Base-T, it is 10101011
(also   called   the   SFD,   start   of   frame   delimiter).   The
incoming data stream, after passing through the polarity
inversion  logic  (which  can  be  turned  on  or  off  under
software   control)   is   compared   to   the   synchronization
pattern. Once a match is found, an internal counter is set
to  zero  and  data  is  shifted  into  a  shift  register.  The
synchronization matching operation is then disabled until
an EOP condition is detected, because the synchronization pattern potentially could be embedded in
the data stream as valid data. The  clock/data  separation  circuit  performs  Manchester
decoding and NRZI decoding. In addition, bit unstuffing is
performed after the NRZI decoding for the USB bus. This
means every bit after a series of six consecutive ones is
dropped. For   10Base-T   Ethernet   operation,   each   SERDES   is
equipped with a squelch circuit for discriminating between
noise,   link   pulses,   and   data.   Link   pulses   are   sent
periodically  to  keep  the  channel  open  when  no  data  is
being transmitted. The squelch circuit handles link pulse
detection, link pulse polarity detection, carrier sense, and
EOP detection. For UART operation, two internal divide-by-16 circuits are
used.   Based   on   the   clock   source   (either   internal   or
external), the receive section and the transmit section use
two  divided-by-16  clocks  that  potentially  can  be  out  of
phase.   This   is   due   to   the   nature   of   the   UART   bus
transfers. The receive logic, based on the 16x bit clock
(the   clock   source   chosen   by   user),   will   sample   the
incoming  data  for  an  falling  edge.  Once  the  edge  is
detected,  the  receive  logic  counts  8  clock  cycles  and
samples  the  number  of  bits  specified  in  the  SxRCNT
register using the bit clock (which is obtained by dividing
the clock source by 16). Table 5-7  SERDES Port Pin Usage SERDES1 Signal Port Pin SERDES2 Signal Port Pin Description S1CLK RE0 S2CLK RF0 Serial clock S1RXP RE1 S2RXP RF1 Plus-side differential input S1RXM RE2 S2RXM RF2 Minus-side differential input S1RXD RE3 S2RXD RF3 Serial data S1TXPE S1OE RE4 S2TXPE S1OE RF4 Plus-side differential output with pre-emphasis, or
output enable for external transceiver S1TXP RE5 S2TXP RF5 Plus-side differential output S1TXM RE6 S2TXM RF6 Minus-side differential output S1TXME RE7 S2TXME RF7 Minus-side differential output with pre-emphasis S1Rx+ RG5 S2Rx+ RG7 Plus-side analog differential input S1Rx- RG4 S2Rx- RG6 Minus-side analog differential input