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IP2022 Data Sheet
TxCFG2H/TxCFG2L Register
Selects capture input trigger edges, prescaler setting, and
other configuration settings.
•
PS3:0—Timer prescaler divisor, as shown in Table 5-
5.
•
TOUTSET—set this bit to force TxOUT high. Clearing
this bit has no effect. This bit always reads as 0.
•
TOUTCLR—set this bit to force TxOUT low. Clearing
this bit has no effect. This bit always reads as 0.
•
CPI2CPI1—set this bit to tie internally the TxCPI2 in-
put to the TxCPI1 input. When this bit is set, the exter-
nal TxCPI1 input is used to trigger both capture
functions, for measuring both the duty cycle and the
period of an external signal. This leaves the pin as-
signed to the TxCPI2 input free to be used as a gen-
eral-purpose I/O port pin.
•
CPI2EDG1:0—these bits select the sensitive edge for
the TxCPI2 input. 00 selects falling edges, 01 selects
rising edges, 10 and 11 select any edge.
•
CPI1EDG1:0—these bits select the sensitive edge for
the TxCPI1 input. 00 selects falling edges, 01 selects
rising edges, 10 and 11 select any edge.
TCTRL Register
Unlike the other timer control registers, one TCTRL
register is used to synchronize both timers. Setting the
TxRST bit clears the TxCNTH/TxCNTL register pair and
the
prescaler
counter,
which
allows
global
synchronization of all timers on the device. There are also
individual timer interrupt-enable bits.
•
T2IE—Timer 2 global interrupt enable. Set to enable
timer interrupts, clear to disable.
•
T1IE—Timer 1 global interrupt enable. Set to enable
timer interrupts, clear to disable.
•
T2RST—Timer 2 reset. Set this bit to clear Timer 2
and its prescaler.
•
T1RST—Timer 1 reset. Set this bit to clear Timer 1
and its prescaler.
15
12
11
8
7
6
5
4
3
2
1
0
Reserved
PS3:0
Figure 5-9 TxCFG2H/TxCFG2L Register
Table 5-5 Prescaler Divisor
PS3:0
Prescaler Divisor
0000
1
0001
2
0010
4
0011
8
0100
16
0101
32
0110
64
0111
128
1000
256
1001
512
1010
1024
1011
2048
1100
4096
1101
8192
1110
16384
1111
32768
15
6
5
4
3
2
1
0
Reserved
Figure 5-10 TCTRL Register
