58 www.ubicom.com IP2022 Data Sheet This mode also features an output-compare function. The
TxCMP1H/TCMP1L   register    is    constantly    compared
against the internal counter/timer. When the counter/timer
reaches  the  value  of  the  TxCMP1H/TxCMP1L  register
minus one, at the next counter clock the TxOUT output is
toggled. The TxOUT output, if enabled via the OEN bit,
can be driven high or low by writing to the TOUTSET and
TOUTCLR bits in the TxCFG2 register. An interrupt can
be enabled for this event. 5.4.2 T1 and T2 Timer Pin Assignments The following table lists the I/O port pins associated with
the Timer T1 and Timer T2 I/O functions. 5.4.3 T1 and T2 Timer Registers Each   timer   has   six   16-bit   register   pairs,   which   are
accessed as 8-bit registers in the special-purpose register
space.  There  is  also  one  8-bit  register  shared  by  both
timers. TxCNTH/TxCNTL Register The TxCNTH/TxCNTL register indicates the value of the
counter/timer   and   increments   synchronously   with   the
rising edge of the system clock. This register is read-only.
The timer counter may be cleared by writing to the TxRST
bit in the TCTRL register. Reading the TxCNTL register returns the least-significant
8 bits of the internal TxCNT counter and causes the most-
significant  8  bits  of  the  counter  to  be  latched  into  the
TxCNTH   register.   This   allows   software   to   read   the
TxCNTH register later and still be assured of atomicity. TxCAP1H/TxCAP1L Register The  TxCAP1H/TxCAP1L  register  captures  the  value  of
the counter/timer when the TxCPI1 input is triggered. This
register is read-only. Reading    the    TxCAP1L    register    returns    the    least-
significant 8 bits of an internal capture register and causes
the most-significant 8-bits of the register to be latched into
the TxCAP1H register. This allows software to read the
TxCAP1H register later and still be assured of atomicity. TxCMP1H/TxCMP1L Register In  Capture/Compare  mode,  the  TxOUT  output  pin  is
toggled (if enabled by the OEN bit in the TxCFG1 register)
when  the  counter/timer  increments  to  the  value  in  the
TxCMP1 register. In this mode, the value written to the
TxCMP1 register takes effect immediately. Writing to the TxCMP1L register causes the value to be
stored  in  the  TxCMP1L  register  with  no  other  effect.
Writing   to   the   TxCMP1H   register   causes   an   internal
compare register to be loaded with a 16-bit value in which
the low 8 bits come from the TxCMP1L register and high
8 bits come from the value being written to the TxCMP1H
register.  Software  should  write  the  TxCMP1L  register
before writing the TxCMP1H register, because writing to
the TxCMP1H register is used as an indication that a new
compare value has been written. Writing to the TxCMP1H
register  is  required  for  the  new  compare  value  to  take
effect. In PWM mode, the 16-bit number latched into the
internal  compare  register  by  writing  to  the  TxCMP1H
register does not take effect until the end of the current
PWM cycle. Reading the TxCMP1H or TxCMP1L registers returns the
previously written value whether or not the value stored in
these   registers   has   been   transferred   to   the   internal
compare register by writing to the TxCMP1H register. TxCAP2H/TxCAP2L or TxCMP2H/TxCMP2L Register This   register   may   be   called   the   TxCAP2H/TxCAP2L
register or TxCMP2H/TxCMP2L register. In PWM mode, this register determines the period of the
PWM signal. In this mode, this register is both readable
and writeable. However, on writes the value is not applied
until the end of the current PWM cycle. Writing to the TxCAP2L register causes the value to be
stored  in  the  TxCAP2L  register  with  no  other  effect.
Writing   to   the   TxCAP2H   register   causes   an   internal
compare register to be loaded with a 16-bit value in which
the low 8 bits come from the TxCAP2L register and the          Table 5-4  Timer T1/T2 Pin Assignments
I/O Pin Timer T1/T2 Function RA0 Timer T1 Capture 1 Input RA1 Timer T1 Capture 2 Input RA2 Timer T1 External Event Clock Source RA3 Timer T1 Output RB0 Timer T2 Capture 1 Input RB1 Timer T2 Capture 2 Input RB2 Timer T2 External Event Clock Source RB3 Timer T2 Output