IP2022 Data Sheet www.ubicom.com 57 5.4.1 Timers T1, T2 Operating Modes Each  timer  can  be  configured  to  operate  in  one  of  the
following modes: • Pulse-Width Modulation (PWM) • Timer • Capture/Compare PWM Mode In  PWM  Mode,  the  timer  can  generate  a  pulse-width
modulated signal on its output pin, TxOUT. The period of
the PWM cycle (high + low) is specified by the value in the
TxCAP2H/TxCAP2L register. The high time of the pulse is
specified   by   the   value   in   the   TxCMP1H/TxCMP1L
register. PWM mode can be used to generate an external clock
signal that is synchronous to the IP2022 system clock. For
example,  by  loading  TxCMP1H/TxCMP1L  with  1  and
TxCAP2H/TxCAP2L with 2, a symmetric 50-MHz external
clock can be generated from a 100 MHz system clock. In
some    applications,    this    can    eliminate    crystals    or
oscillators  required  to  produce  clock  signals  for  other
components in the system. The  16-bit  counter/timer  counts  upward.  After  reaching
the   value   stored   in   the   TxCMP1H/TxCMP1L   register
minus one, at the next clock edge the TxOUT pin is driven
low.  The  counter/timer  is  unaffected  by  this  event  and
continues to increment. After reaching the value stored in
the TxCAP2H/TxCAP2L register minus one, at the next
clock  edge  the  timer  is  cleared.  When  the  counter  is
cleared,  the  TxOUT  output  is  driven  high,  unless  the
TxCMP1H/TxCMP1L register is clear, in which case the
TxOUT pin is driven low. There are two special cases. When                                                                                                         the
TxCMP1H/TxCMP1L register is clear, the TxOUT pin is
driven  with  a  continuous  low,  corresponding  to  a  duty-
cycle of 0%. When the value in the TxCMP1H/TxCMP1L
register is equal to the value in the TxCAP2H/TxCAP2L
register,  the  TxOUT  output  is  driven  with  a  continuous
high, corresponding to a duty-cycle of 100%. The   behavior   of   the   timers   when   the   value   in   the
TxCMP1H/TxCMP1L register are greater than the value
in the TxCAP2H/TxCAP2L register is undefined. The timer is glitch-free no matter when                                                                                                         the
TxCMP1H/TxCMP1L register or the TxCMP2H/TxCMP2L
register are changed relative to the value of the internal
counter/timer. The new duty cycle or period values do not
take effect until the current PWM cycle is completed (the
counter/timer is reset). Interrupts, if enabled through the TxCFG1 register, can be
generated whenever the timer output is set or cleared. If
the TxCMP1H/TxCMP1L register is clear, or if the value in
the TxCMP1H/TxCMP1L register is equal to the value in
the TxCAP2H/TxCAP2L register, an interrupt is generated
each time the counter/timer is reset to zero. In  PWM  mode,  the  Capture  1  input  remains  active  (if
enabled by the CPI1EN bit in the TxCFG1 register) and,
when triggered, captures the current counter/timer value
into the TxCAP1 register. The multifunction timers can be configured to interrupt on
a  Capture  1  event  and  reset  the  counter/timer  on  the
event.  For  PWM  operation  without  Capture  1,  software
must disable the Capture 1 input by clearing the CPI1EN
bit in the TxCFG1 register. Timer Mode This  is  not  a  separate  timer  mode  (from  the  hardware
point of view), but is a conceptual mode for programmers.
It  is  the  PWM  mode,  except  that  software  disables  the
timer output by clearing the OEN bit in the TxCFG register. Capture/Compare Mode In  Capture/Compare  mode,  one  or  both  of  the  timer
capture inputs (TxCPI1 and TxCPI2) may be used. Their
pin  functions  must  be  enabled  in  the  TxCFG1  register.
Each capture input can be programmed in the TxCFG2
register to trigger on a rising edge, falling edge, or both
rising and falling edges. When  a  trigger  event  occurs  on  either  capture  pin,  the
current  value  of  the  counter/timer  is  captured  into  the
TxCAP1H/TxCAP1L register or the TxCAP2H/TxCAP2L
register for that input pin. The counter/timers can also be configured to reset on a
TxCPI1  input   event,  in  which  case  the  value  of  the
counter/timer   before   it   was   reset   is   captured   in   the
TxCAP1H/TxCAP1L   register   and   the   counter/timer   is
reset  to  zero.  This  mode  is  useful  for  measuring  the
frequency  (or  width)  of  external  signals.  By  using  both
capture inputs and configuring them for opposite edges,
the duty cycle of a signal can also be measured. To avoid
wasting I/O port pins in this configuration, the CPI2CPI1
bit in the TxCFG1 register is provided to internally tie the
TxCPI1  and  TxCPI2  inputs  together,  which  frees  the
TxCPI2 pin to be used as a general-purpose I/O port pin. An interrupt can be generated for any capture event and
for counter/timer overflows.