IP2022 Data Sheet www.ubicom.com 55 Figure 5-5  Real-Time Timer Block Diagram The   real-time   timer   is   readable   and   writable   as   the
RTTMR register. The control and status register for the
timer is the RTCFG register, as shown in Figure 5-6. The
Real-Time Timer should be enabled before its interrupt is
enabled. • RTEN—set to enable the Real-Time Timer, clear to disable. When disabled, clocking is inhibited to save
power. • RTPS3:0—prescaler divisor, as shown in Table 5-3. • RTSS—selects  the  clock  source  (see  Figure  3-16). Set for RTCLK, clear for the pre-PLL clock. • RTIE—set to enable Real-Time Timer overflow inter- rupts, clear to disable interrupts. • RTIF—set on Real-Time Timer overflow. This bit goes high two cycles after the actual overflow occurs. The RTEOS bit in the XCFG register selects the sampling
mode for the external input. If the RTEOS bit is set, the external input is over-sampled
with  the  system  clock.  The  CPU  can  always  read  the
value in the RTTMR register, however, the system clock
must be at least twice the frequency of the external input.
If the system clock source is changed to RTCLK or turned
off, then the RTEOS bit must be clear for the Real-Time
Timer to function. If the RTEOS bit is clear then the external input directly
clocks     the     Real-Time    Timer    (i.e.    RTCLK     is    not
oversampled). The Real-Time Timer will always function
whether the clock input is synchronous or asynchronous.
However, the CPU cannot reliably read the value in the
RTTMR register unless the RTCLK clock is synchronous
to the system clock. If the value in the RTTMR register does not need to be
used by the CPU (i.e. only the interrupt flag is of interest)
then   the   RTEOS   bit   can   be   clear   (i.e.   RTCLK   not
oversampled)   which   allows   the   Real-Time   Timer   to
function for any configuration of the system clock. If the value in the RTTMR register needs to be used by the
CPU, but the Real-Time Timer is not required to function
when the system clock is set to RTCLK or turned off, then 515-015.eps RTTMR
Register RTIE RTIF Real-Time
Timer Interrupt    15-Bit
Prescaler  OSC
Clock RTCLK RTEN RTPS 3:0 RTSS Data Bus 8 7 6 3 2 1 0 RTEN RTPS3:0 RTSS   RTIE RTIF Figure 5-6  RTCFG Register Table 5-3  Real-Time Timer Prescaler Divisor RTPS3:0 Divisor 0000 1 0001 2 0010 4 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256 1001 512 1010 1024 1011 2048 1100 4096 1101 8192 1110 16384 1111 32768 Table 5-3  Real-Time Timer Prescaler Divisor (continued) RTPS3:0 Divisor