IP2022 Data Sheet www.ubicom.com 5 1.2.3 Low-Power Support Particular  attention  has  been  paid  to  minimizing  power
consumption. For example, an on-chip PLL allows use of
a lower-frequency external source (e.g., an inexpensive 2
MHz crystal oscillator can be used to produce a 100 MHz
on-chip  clock),  which  reduces  both  power  consumption
and EMI. In addition, software can change the execution
speed of the CPU to reduce power consumption, and a
mechanism  is  provided  for  automatically  changing  the
speed  on  entry  and   return  from  an  interrupt  service
routine.  The  speed  instruction  specifies  power-saving
modes that include a clock divisor between 1  and  128.
This divisor only affects the clock to the CPU core, not the
timers.  The  speed  instruction  also  specifies  the  clock
source  (OSC1  clock,  RTCLK  oscillator,  or  PLL  clock
multiplier),   and   whether   to   disable   the   OSC1   clock
oscillator  or  the  PLL.  The  speed  instruction  executes
using the current clock divisor. 1.2.4 Memory The IP2022 CPU executes from a 32K × 16 flash program
memory and an 8K × 16 RAM program/data memory. In
addition, the ability to write into the program flash memory
allows flexible non-volatile data storage.  An interface  is
available for up to 128K bytes of external memory. The
maximum execution rate is 30 MIPS from flash memory
and 100 MIPS from RAM. Speed-critical routines can be
copied  from  the  flash  memory  to  the  RAM  for  faster
execution.  The  IP2022  has  a  mechanism  for  in-system
programming  of  its  flash  and  RAM  program  memories
through a four-wire SPI interface, and software has the
ability to reprogram the program memories at run time.
This allows the functionality of a device to be changed in
the field over the Internet. 1.2.5 Instruction Set The    IP2022    instruction    set,    using    16-bit    words,
implements a rich set of arithmetic and logical operations,
including signed and unsigned 8-bit × 8-bit integer multiply
with a 16-bit product. 1.2.6 The ipModule Concept The ipModule concept enables the “software system-on-
a-chip” approach. An ipModule is a                                                                                              software
implementation of an interface, protocol, or other function
that replaces traditional hardware. This takes advantage
of   the   Ubicom   architecture’s   high   performance   and
deterministic   nature   to   produce   the   same   results   as
hardware, but with much greater system design flexibility.
Having  functionality  implemented  as  pre-built  software
modules   allows   the   IP2022   to   be   programmed   and
reprogrammed    at    any    time    in    the    design    and
manufacturing   cycle,   and   even   in   the   field   over   the
Internet. The  speed  and  flexibility  of  the  Ubicom  architecture,
together   with   the   availability   of   Internet   connectivity
software modules, simultaneously address a wide range
of engineering and product development concerns. They
decrease  the  product  development  cycle  dramatically,
shortening time to production to as little as a few weeks. Ubicom’s  ipModules  give  system  designers  a  choice  of
ready-made solutions, or a head start on developing their
own  peripherals.  With  ipModules  handling  established
functions,  design  engineers  can  concentrate  on  adding
value to other areas of the application. Overall, the ipModule concept provides such benefits as
simpler    hardware    architecture,    reduced    component
count, fast time to market, increased flexibility in design,
application customization, and system cost reduction. Some examples of ipModules are: • Ethernet and USB network interfaces • Communication interfaces such as GPSI, I²C™, Mi-
crowire™, SPI, and UART • Internet connectivity protocols, such as UDP, TCP/IP,
ARP, DHCP, HTTP, SMTP, and POP3