IP2022 Data Sheet www.ubicom.com 49 • FRDTC1:0—the number of CPU core cycles for read-
ing the flash memory with an iread instruction must
be specified to prevent the flash memory access time
from being exceeded. Because the CPU core speed
may  change,  the  value  programmed  in  these  bits
should be appropriate for the fastest speed that might
be used (typically, the faster of the mainline code and
the  interrupt  service  routine).  The  FRDTC1:0  bits
specify the number of CPU core clock cycles required
for read access, as shown in Table 4-10. • FWRT3:0—the flash memory erase and write timing
is  derived  from  the  CPU  core  clock  through  a  pro-
grammable    divider,    which    is    controlled    by    the
FWRT3:0 bits. The time base must be 1 to 2 micro-
seconds. Below 1 microsecond, the flash memory will
be underprogrammed, and data retention is not guar-
anteed. Above 2 microseconds, the flash memory will
be overprogrammed, and reliability is not guaranteed.
Because the minimum flash write clock divisor is 2,
the minimum clock frequency for self-programming is
1 MHz. The range of values for FWRT3:0 is shown in
Table 4-11. 4.7.2 Interrupts During Flash Operations Before starting a flash write or erase operation, the flash
write timing compensation must be set up properly for the
current speed. The CPU core clock is the time base for the
flash write timing compensation, so it is critical that the
CPU core clock speed is not changed during a flash write
or erase operation. Interrupts may be taken during a flash
write or erase operation, if the INTSPD register is set up
so the speed does not change when an interrupt occurs. If the flash read timing compensation is set up for a clock
divisor of 1 (i.e. fastest speed), interrupts will not cause iread instructions to fail, so no special precautions need to be taken to avoid violating the flash read access time. Table 4-9  Flash Execution Timing FRDTS1:0  System Clock Cy-
cles For Each CPU Core Clock Cycle System Clock Frequency (MHz) 00 1 0–30 01 2 30–60 10 3 60–90 11 4 90–120 Table 4-10  Flash Read Timing FRDTC1:0    System Clock
Cycles Per Flash Access System Clock Frequency (MHz) 00 1 0–30 01 2 30–60 10 3 60–90 11 4 90–120 Table 4-11  Flash Write Timing FWRT3:0   Flash Write
Clock Divisor  CPU Core Clock
Frequency (MHz) 0000 2 1–2 0001 3 2–3 0010 4 3–4 0011 6 4–6 0100 8 6–8 0101 12 8–12 0110 16 12–16 0111 24 16–24 1000 32 24–32 1001 48 32–48 1010 64 48–64 1011 96 64–96 1100 128 96–100 1101 192 Reserved 1110 256 Reserved 1111 384 Reserved