48 www.ubicom.com IP2022 Data Sheet Blocking  instructions   take   4  cycles  to  complete,   and
prevent  other  instructions  from  executing.  Non-blocking
instructions occupy the CPU pipeline for only one cycle,
but  they  launch  a  multi-cycle  operation  which  is  not
complete until indicated by the FBUSY bit in the XCFG
register becoming clear. Read and write operations that involve program memory
use two registers. The DATAH/DATAL register is a 16-bit
data buffer used for loading or unloading data in program
memory.  The  ADDRX/ADDRH/ADDRL  register  holds  a
24-bit  address  used  to  specify  a  location  in  program
memory.   Like   the   other   pointer   registers   (IPH/IPL,
DPH/DPL, and SPH/SPL), addition to the low byte of the
register that results in carry will cause the high part of the
register (ADDRX/ADDRH) to be incremented. Subtraction
from the low byte of the register that results in borrow will
cause the high part of the register to be decremented. Software can use the FBUSY bit to check that a previous
flash memory operation has completed before executing
another  instruction  that  accesses  flash  memory,  before
jumping  or  calling  program  code  in  flash  memory,  and
before changing the CPU core speed. Software must not
attempt to execute out of flash memory while the FBUSY
bit is set, because the flash memory is unreadable during
that  time.  Code  which  reads,  writes,  or  erases  flash
memory  must  execute  from  program  RAM,  not  flash
memory. The CPU core speed must not change while a
flash   memory   read,   write,   or   erase   operation   is   in
progress. Software must wait at least three cycles before
checking   the   FBUSY   bit   for   completion   of   the   flash
operation. It is not necessary to check the FBUSY bit if
enough  cycles  are  allowed  for  the  flash  operation  to
complete. Unlike  RAM,  flash  memory  requires  an  explicit  erase
operation before being written. The ferase instruction is
used   to   erase   a   512-byte   (256-word)   block   of   flash
memory.  After  the  block  has  been  erased,  individual
words  can  be  written  with  the  fwrite  instruction.  For
example,   an   ferase   instruction   executed   on   any
address  from  0x10000  to  0x100FE  erases  the  whole
block spanning those addresses. The self-programming
instructions have no access to the flash memory bits used
to implement the configuration block. 4.7.1 Flash Timing Control The  FCFG register controls  the  timing  of  flash memory
operations. Figure 4-15 shows the FCFG register. • FRDTS1:0—the CPU core clock while executing from
flash program memory must not exceed 30 MHz, oth-
erwise  unreliable  operation  may  result.  The  IP2022
automatically increases the number of system clock
cycles for each CPU core clock cycle when executing
from  flash,  but  it  is  the  responsibility  of  software  to
load the FRDTS1:0 bits appropriately for the operat-
ing  frequency,  as  shown  in  Table 4-9.  The  actual
speed will be the slower of the speed indicated in the
SPDREG  register  and  the  speed  specified  by  the
FRDTS1:0 bits. The previous CPU core clock divisor
is  reinstated  when  jumping  back  to  program  RAM
from program flash memory. Table 4-8  Instructions Used for Self-Programming Instruction  Executed From
RAM to Operate On Program RAM  Executed From
RAM to Operate On Flash Memory  Executed From
Flash to Operate On Program RAM  Executed From
Flash to Operate On Flash Memory  Executed While
FWP Bit in XCFG
Register is Clear (FWP = 0) iread
ireadi Blocking Non-Blocking Blocking Blocking N/A iwrite
iwritei Blocking nop Blocking nop N/A fwrite nop Non-Blocking nop nop nop ferase nop Non-Blocking nop nop nop 7 6 5 4 3 0 FRDTS1:0 FRDTC1:0                                               FWRT3:0
Figure 4-15  FCFG Register