40 www.ubicom.com IP2022 Data Sheet Program Control Instructions A   program   control   instruction   alters   the   flow   of   the
program by changing the contents of the program counter.
Included in this category are the jump, call, return-from-
subroutine, and interrupt instructions. The jmp instruction has a single operand that specifies
the entry point at which to continue execution. The entry
point  is  typically  specified  in  assembly  language  with  a
label, as in the following code example: If the carry bit is set to 1, the jmp instruction is executed
and program execution continues where the do_carry
label appears in the program. The call instruction works in a similar manner, except
that it saves the contents of the program counter before
jumping to the new address. It calls a subroutine that is
terminated by a ret instruction, as shown in the following
code example: Returning from a subroutine restores the saved program
counter   contents,   which   causes   program   to   resume
execution  with  the  instruction  immediately  following  the call   instruction   (a   nop   instruction,   in   the   above example) A program memory  address contains 16 bits. The  jmp
and call instructions specify only the lowest thirteen bits
of the jump/call address. The upper 3 bits come from the
PA2:0  bits  of  the  STATUS  register.  An  indirect  relative
jump can be accomplished by adding the contents of the
W  register  to  the  PCL  register  (i.e.  an  add   pcl,w
instruction). Program  control  instructions  such  as  jmp,  call,  and ret  alter  the  normal  program  sequence.  When  one  of these instructions is executed, the execution pipeline is
automatically cleared of pending instructions and refilled
with   new   instructions,   starting   at   the   new   program
address.  Because  the  pipeline  must  be  cleared,  three
clock cycles are required for execution, one to execute the
instruction and two to reload the pipeline. System Control Instructions A system control instruction performs a special-purpose
operation that sets the operating mode of the device or
reads  data  from  the  program  memory.  Included  in  this
category are the following types of instructions: • speed—changes  the  CPU  core  speed  (for  saving power) • break—enters debug mode • page—writes the PA2:0 bits in the STATUS register • loadh/loadl—loads a 16-bit pointer into the DPH and DPL registers • iread/ireadi—reads a word from external mem- ory, program flash memory, or program RAM • iwrite/iwritei—writes a word to external mem- ory or program RAM • fwrite—writes a word to flash program memory • ferase—erases a block of flash program memory • cwdt—clears the Watchdog Timer 4.3 Instruction Pipeline An  instruction  goes  through  a  four-stage  pipeline  to  be
executed, as shown in Figure 4-12. The first instruction is
fetched from the program memory on the first clock cycle.
On the second clock cycle, the first instruction is decoded
and  a  second  instruction  is  fetched.  On  the  third  clock
cycle,   the   first   instruction   is   executed,   the   second
instruction is decoded, and a third instruction is fetched.
On the fourth clock cycle, the first instruction’s results are
written   to   its   destination,   the   second   instruction   is
executed,  the  third  instruction  is  decoded,  and  a  fourth
instruction is fetched. Once the pipeline is full, instructions
are executed at the rate of one per clock cycle. snb status,0   ;test the carry bit jmp do_carry   ;jump to do_carry routine ;if C = 1 ...
do_carry: ;jump destination label ... ;execution continues here call add_2bytes   ;call subroutine ;add_2bytes nop ;execution returns to
;here after the
;subroutine is finished ...
add_2bytes: ;subroutine label ... ;subroutine code goes
;here ret ;return from subroutine Stage Cycle 1 Cycle 2 Cycle 3 Cycle 4 Fetch Instruction 1  Instruction 2  Instruction 3  Instruction 4 Decode Instruction 1  Instruction 2  Instruction 3 Execute Instruction 1  Instruction 2 Write Instruction 1 Figure 4-12  Pipeline Execution